Patents by Inventor Christian Bergeron
Christian Bergeron has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11139269Abstract: An electronic package and a method of manufacture includes a substrate having an upper surface with a trench formed in a bridge region. First pads are arranged on the upper surface of the substrate, outside of the bridge region, and a bridge is positioned in the trench. A plurality of second pads are arranged on an upper surface of the bridge. A plurality of pillars are electrically coupled to the plurality of second pads. Two or more semiconductor chips are positioned in a side-by-side proximal arrangement overlaying the bridge and the substrate. A first semiconductor chip is joined to the bridge, then a second semiconductor chip is joined to the bridge, followed by attaching the chip-bridge assembly to the substrate with the bridge positioned within the substrate trench. Each of the two or more semiconductor chips have first electrical connections including bumps, and second electrical connections including third pads.Type: GrantFiled: January 25, 2020Date of Patent: October 5, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kamal K. Sikka, Paul S. Andry, Yang Liu, Pascale Gagnon, Christian Bergeron, Maryse Cournoyer
-
Publication number: 20210233892Abstract: An electronic package and a method of manufacture includes a substrate having an upper surface with a trench formed in a bridge region. First pads are arranged on the upper surface of the substrate, outside of the bridge region, and a bridge is positioned in the trench. A plurality of second pads are arranged on an upper surface of the bridge. A plurality of pillars are electrically coupled to the plurality of second pads. Two or more semiconductor chips are positioned in a side-by-side proximal arrangement overlaying the bridge and the substrate. A first semiconductor chip is joined to the bridge, then a second semiconductor chip is joined to the bridge, followed by attaching the chip-bridge assembly to the substrate with the bridge positioned within the substrate trench. Each of the two or more semiconductor chips have first electrical connections including bumps, and second electrical connections including third pads.Type: ApplicationFiled: January 25, 2020Publication date: July 29, 2021Inventors: Kamal K. Sikka, Paul S. Andry, Yang Liu, Pascale Gagnon, Christian Bergeron, Maryse Cournoyer
-
Publication number: 20200315294Abstract: The present disclosure concerns a sock-lined footwear upper defining a foot-receiving cavity and comprising a sock having an outer surface and an inner surface at least partially delimiting the foot-receiving cavity and comprising a heel counter area; an outer layer covering at least partially the outer surface of the sock; and a heel pad at least partially secured to the inner surface of the sock in the heel counter area thereof. The present disclosure also concerns such a heel pad, an item of sock-lined footwear comprising such an upper and a method for manufacturing such an item of sock-lined footwear.Type: ApplicationFiled: April 3, 2020Publication date: October 8, 2020Inventors: Alexandre Bergeron, Christian Bergeron
-
Patent number: 10784202Abstract: A package and system for high-density chip-to-chip interconnection is provided. Embodiments of the present invention utilizes a plurality of circuit dies including a laminate substrate adjacent to the plurality of circuit dies. It also includes a conductive spacer disposed between the laminate substrate and one of the plurality of circuit dies, a silicon bridge and a conductive interposer disposed between the laminate substrate and the plurality of dies and adjacent to the conductive spacer. Furthermore the embodiment of this present invention can include a top layer of a printed circuit board (PCB) coupled with a bottom layer of the laminate substrate. The conductive spacer comprises, at least of, a laminate, organic or copper material.Type: GrantFiled: December 1, 2017Date of Patent: September 22, 2020Assignee: International Business Machines CorporationInventors: Francois Arguin, Luc Guerin, Maryse Cournoyer, Steve E. Whitehead, Jean Audet, Richard D. Langlois, Christian Bergeron, Pascale Gagnon, Nathalie Meunier
-
Publication number: 20190350307Abstract: Safety footwear, a metatarsal guard for safety footwear, and a method for manufacturing a metatarsal guard comprising: a guard body sized and shaped to cover at least partially a dorsal surface of a wearer's foot, the guard body including: a shielding layer made of a rigid material, the shielding layer further including a first bonding surface; an extension panel extending forwardly from the guard body, the extension panel including a second bonding surface, the extension panel being disposed against the shielding body such that the first and second bonding surfaces are superposed over each other, the extension panel being overmolded over the shielding layer such that the extension panel is bonded with the shielding layer along the superposed first and second bonding surfaces.Type: ApplicationFiled: May 13, 2019Publication date: November 21, 2019Inventor: Christian Bergeron
-
Publication number: 20190172787Abstract: A package and system for high-density chip-to-chip interconnection is provided. Embodiments of the present invention utilizes a plurality of circuit dies including a laminate substrate adjacent to the plurality of circuit dies. It also includes a conductive spacer disposed between the laminate substrate and one of the plurality of circuit dies, a silicon bridge and a conductive interposer disposed between the laminate substrate and the plurality of dies and adjacent to the conductive spacer. Furthermore the embodiment of this present invention can include a top layer of a printed circuit board (PCB) coupled with a bottom layer of the laminate substrate. The conductive spacer comprises, at least of, a laminate, organic or copper material.Type: ApplicationFiled: December 1, 2017Publication date: June 6, 2019Inventors: Francois Arguin, Luc Guerin, Maryse Cournoyer, Steve E. Whitehead, Jean Audet, Richard D. Langlois, Christian Bergeron, Pascale Gagnon, Nathalie Meunier
-
Patent number: 8514386Abstract: A method for verifying the internal microstructure of interconnects in flip-chip applications includes providing a microelectronic assembly comprising the following: a substrate hosting an array of flip-chip attach pads and one or more process control pads; a flip chip having an array of solder bumps in contact with the array of flip-chip attach pads; and one or more representative solder bumps contacting the one or more process control pads. The representative solder bumps have a substantially similar or identical chemical composition as the array of solder bumps. A reflow cycle is then applied to the microelectronic assembly to melt and solidify the array of solder bumps on the flip-chip attach pads and melt and solidify the representative solder bumps on the process control pads. The surface texture of the representative solder bumps is then optically inspected to determine an internal microstructure of the array of solder bumps.Type: GrantFiled: May 25, 2011Date of Patent: August 20, 2013Assignee: International Business Machines CorporationInventors: Christian Bergeron, Pascal Blais, Clement Fortin, Luc Guerin
-
Publication number: 20120300220Abstract: A method for verifying the internal microstructure of interconnects in flip-chip applications includes providing a microelectronic assembly comprising the following: a substrate hosting an array of flip-chip attach pads and one or more process control pads; a flip chip having an array of solder bumps in contact with the array of flip-chip attach pads; and one or more representative solder bumps contacting the one or more process control pads. The representative solder bumps have a substantially similar or identical chemical composition as the array of solder bumps. A reflow cycle is then applied to the microelectronic assembly to melt and solidify the array of solder bumps on the flip-chip attach pads and melt and solidify the representative solder bumps on the process control pads. The surface texture of the representative solder bumps is then optically inspected to determine an internal microstructure of the array of solder bumps.Type: ApplicationFiled: May 25, 2011Publication date: November 29, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christian Bergeron, Pascal Blais, Clement Fortin, Luc Guerin
-
Patent number: 6333491Abstract: Circuit chips, such as known good die (KGD) chips, are removed from an assembly including a plurality of circuit chips attached to at least one chip carrier, or substrate. The substrate is held within a top plate with the circuit chips positioned within successive chip cavities within a bottom plate. Each chip cavity includes a load surface separated by a cascade effect pitch with respect to adjacent chip cavities. A cascade effect shear force is sequentially applied to the circuit chips to remove them from the substrate. The chips may be heated to a temperature facilitating shear within a temperature range at which solder connections are solid, and the chips further heated following disassembly to a temperature at which the solder is liquid to facilitate reforming the solder for subsequent attachment of the chip into an electronic device.Type: GrantFiled: November 1, 2000Date of Patent: December 25, 2001Assignee: International Business Machines CorporationInventors: Christian Bergeron, Raymond Lord, Mario Racicot
-
Patent number: 6320163Abstract: Circuit chips, such as known good die (KGD) chips, are removed from an assembly including a plurality of circuit chips attached to at least one chip carrier, or substrate. The substrate is held within a top plate with the circuit chips positioned within successive chip cavities within a bottom plate. Each chip cavity includes a load surface separated by a cascade effect pitch with respect to adjacent chip cavities. A cascade effect shear force is sequentially applied to the circuit chips to remove them from the substrate. The chips may be heated to a temperature facilitating shear within a temperature range at which solder connections are solid, and the chips further heated following disassembly to a temperature at which the solder is liquid to facilitate reforming the solder for subsequent attachment of the chip into an electronic device.Type: GrantFiled: December 13, 2000Date of Patent: November 20, 2001Assignee: International Business Machines CorporationInventors: Christian Bergeron, Raymond Lord, Mario Racicot
-
Publication number: 20010000208Abstract: Circuit chips, such as known good die (KGD) chips, are removed from an assembly including a plurality of circuit chips attached to at least one chip carrier, or substrate. The substrate is held within a top plate with the circuit chips positioned within successive chip cavities within a bottom plate. Each chip cavity includes a load surface separated by a cascade effect pitch with respect to adjacent chip cavities. A cascade effect shear force is sequentially applied to the circuit chips to remove them from the substrate. The chips may be heated to a temperature facilitating shear within a temperature range at which solder connections are solid, and the chips further heated following disassembly to a temperature at which the solder is liquid to facilitate reforming the solder for subsequent attachment of the chip into an electronic device.Type: ApplicationFiled: December 13, 2000Publication date: April 12, 2001Inventors: Christian Bergeron, Raymond Lord, Mario Racicot
-
Patent number: 6163014Abstract: Circuit chips, such as known good die (KGD) chips, are removed from an assembly including a plurality of circuit chips attached to at least one chip carrier, or substrate. The substrate is held within a top plate with the circuit chips positioned within successive chip cavities within a bottom plate. Each chip cavity includes a load surface separated by a cascade effect pitch with respect to adjacent chip cavities. A cascade effect shear force is sequentially applied to the circuit chips to remove them from the substrate. The chips may be heated to a temperature facilitating shear within a temperature range at which solder connections are solid, and the chips further heated following disassembly to a temperature at which the solder is liquid to facilitate reforming the solder for subsequent attachment of the chip into an electronic device.Type: GrantFiled: December 13, 1999Date of Patent: December 19, 2000Assignee: International Business Machines CorporationInventors: Christian Bergeron, Raymond Lord, Mario Racicot