Abstract: Technology related to hardware accelerated neural network subgraphs is disclosed. In one example of the disclosed technology, a method for compiling a neural network model is disclosed. The method includes identifying a subgraph of the neural network model to partition from the neural network model. An interface can be inserted between the neural network model and a partitioned version of the identified subgraph. The partitioned version can be adapted to be evaluated with a neural network accelerator. The identified subgraph can be compiled to the neural network accelerator to generate configuration information for the neural network accelerator. The neural network accelerator can be configured with the configuration information to provide an accelerated version of the subgraph.

Abstract: In embodiments of defective code warning resolution analysis, defective code warnings are received, such as code development warnings and/or code execution warnings. The defective code warnings can be grouped into warning groups according to properties of each defective code warning. Each instance of a defective code warning in a warning group can then be determined as one of fixed, suppressed, or ignored. Each instance of the defective code warning in the warning group is also aggregated based on each warning state of fixed, suppressed, or ignored.