Abstract: A bit interleaved time division multiplexer for multinode system is provided and includes a high speed bus, a plurality of aggregate common blocks, a plurality of channel common blocks, and a system controller which selects the aggregate and channel common blocks and which is connected to the bus. Each aggregate common block includes an address recognizer, a recorder for obtaining information according to a first frame format from an aggregate line, supplying an intramultiplexer system address for at least one bit of the obtained information, and sending the information accompanied by the intramultplexer system address onto the high speed bus, and a recorder and transmitter for receiving bits of information from the high speed bus, multiplexing the information according to a second frame format and sending the so-multiplexed information out over an aggregate line.

Abstract: A synchronization technique in which the frame used for synchronization is different from that used for normal data communiction and contains few if any bits other than those used to establish synchronization. At the beginning of data communication, the synchronization frame is stored in one of a pair of memories and this frame is read out of the memory onto a communication channel between the local and remote stations. At the same time, the other memory is used to store the frame that is normally used for data communication. When synchronization is established between the local and remote stations, signal generation shifts from the first memory to the second; and the second memory immediately begins to produce the channel select and overhead signals needed for data communication. Illustratively, the synchronization frame contains less than one hundred bits and in a preferred embodiment a total of forty-eight bits are used for synchronization.

Abstract: A transistorized keying circuit is described which provides for both polar and neutral interfacing. The circuit comprises an oscillator, an AND gate, an exclusive OR gate, a transformer, and two similar output circuits each of which is connected to the secondary of the transformer. The oscillator produces a high frequency binary output signal having an asymmetric duty cycle. The output of the oscillator and a low frequency data signal are applied to the AND gate. The output of the AND gate and another low frequency data signal are applied to the exclusive OR gate whose output is amplified and applied to the primary of the transformer. Each output circuit coupled to the secondary of the transformer comprises a switching transistor for switching a supply voltage onto a transmission line and a peak detector for controlling the operation of the switching transistor.