Patents by Inventor Christian Caillat
Christian Caillat has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240038322Abstract: Apparatuses, methods, and systems for performing sense operations in memory are disclosed. The memory can have a group of memory cells, and circuitry can be configured to perform a sense operation on the group, wherein performing the sense operation includes performing a first sense operation in a first polarity on the group of memory cells to determine a quantity of the memory cells of the group that are in a particular data state, and performing a second sense operation in a second polarity on the group of memory cells to determine a data state of the memory cells of the group. The second polarity is opposite the first polarity, and the second sense operation is a count-based sense operation that uses the determined quantity of memory cells in the particular data state as a counting threshold to determine the data state of the memory cells of the group.Type: ApplicationFiled: July 26, 2022Publication date: February 1, 2024Inventors: Michele Maria Venturini, Umberto Di Vincenzo, Ferdinando Bedeschi, Riccardo Muzzetto, Christophe Vincent Antoine Laurent, Christian Caillat
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Publication number: 20230422471Abstract: Some embodiments include apparatuses and methods of operating such apparatuses. One of such apparatuses includes a data line, a conductive region, and a memory cell including a first transistor and a second transistor. The first transistor includes a first channel region coupled to the data line and the conductive region, a charge storage structure, and a first gate. The second transistor includes a second channel region coupled to the data line and the charge storage structure, and a second gate. The first gate is electrically separated from the second gate and opposite from the second gate in a direction from the first channel region to the second channel region.Type: ApplicationFiled: September 8, 2023Publication date: December 28, 2023Inventors: Eric S. Carman, Durai Vishak Nirmal Ramaswamy, Richard E Fackenthal, Kamal M. Karda, Karthik Sarpatwari, Haitao Liu, Duane R. Mills, Christian Caillat
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Patent number: 11778806Abstract: Some embodiments include apparatuses and methods of operating such apparatuses. One of such apparatuses includes a data line, a conductive region, and a memory cell including a first transistor and a second transistor. The first transistor includes a first channel region coupled to the data line and the conductive region, a charge storage structure, and a first gate. The second transistor includes a second channel region coupled to the data line and the charge storage structure, and a second gate. The first gate is electrically separated from the second gate and opposite from the second gate in a direction from the first channel region to the second channel region.Type: GrantFiled: July 29, 2021Date of Patent: October 3, 2023Assignee: Micron Technology, Inc.Inventors: Eric S. Carman, Durai Vishak Nirmal Ramaswamy, Richard E Fackenthal, Kamal M. Karda, Karthik Sarpatwari, Haitao Liu, Duane R. Mills, Christian Caillat
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Publication number: 20230031904Abstract: Some embodiments include apparatuses and methods of operating such apparatuses. One of such apparatuses includes a data line, a conductive region, and a memory cell including a first transistor and a second transistor. The first transistor includes a first channel region coupled to the data line and the conductive region, a charge storage structure, and a first gate. The second transistor includes a second channel region coupled to the data line and the charge storage structure, and a second gate. The first gate is electrically separated from the second gate and opposite from the second gate in a direction from the first channel region to the second channel region.Type: ApplicationFiled: July 29, 2021Publication date: February 2, 2023Inventors: Eric S. Carman, Durai Vishak Nirmal Ramaswamy, Richard E Fackenthal, Kamal M. Karda, Karthik Sarpatwari, Haitao Liu, Duane R. Mills, Christian Caillat
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Patent number: 10504600Abstract: Apparatus including an array of memory cells and a controller configured to program all memory cells of a grouping of memory cells that are to be respectively programmed to different levels other than a lowest level, corresponding to a lowest data state, to an intermediate level from the lowest level, and to respectively program all the memory cells of the grouping of memory cells that are to be respectively programmed to the different levels other than the lowest level to the different levels other than the lowest level from the intermediate level.Type: GrantFiled: November 12, 2018Date of Patent: December 10, 2019Assignee: Micron Technology, Inc.Inventors: Carmine Miccoli, Christian Caillat, Akira Goda
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Patent number: 10346088Abstract: In one embodiment, an apparatus comprises a controller to determine an erase state of a first memory deck independently from an erase state of a second memory deck, the first memory deck comprising a first plurality of wordlines and a first channel, the first memory deck comprising a first plurality of memory cells that are each coupled to the first channel and a respective one of the first plurality of wordlines; the second memory deck comprising a second plurality of wordlines and a second channel, the second channel coupled to the first channel, the second memory deck comprising a second plurality of memory cells that are each coupled to the second channel and a respective one of the second plurality of wordlines; and determine an erase state of the second memory deck independently from an erase state of the first memory deck.Type: GrantFiled: September 29, 2017Date of Patent: July 9, 2019Assignee: Intel CorporationInventors: Niccolo Righetti, Akira Goda, Violante Moschiano, Christian Caillat, Giuseppina Puzzilli
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Publication number: 20190102104Abstract: In one embodiment, an apparatus comprises a controller to determine an erase state of a first memory deck independently from an erase state of a second memory deck, the first memory deck comprising a first plurality of wordlines and a first channel, the first memory deck comprising a first plurality of memory cells that are each coupled to the first channel and a respective one of the first plurality of wordlines; the second memory deck comprising a second plurality of wordlines and a second channel, the second channel coupled to the first channel, the second memory deck comprising a second plurality of memory cells that are each coupled to the second channel and a respective one of the second plurality of wordlines; and determine an erase state of the second memory deck independently from an erase state of the first memory deck.Type: ApplicationFiled: September 29, 2017Publication date: April 4, 2019Inventors: Niccolo Righetti, Akira Goda, Violante Moschiano, Christian Caillat, Giuseppina Puzzilli
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Publication number: 20190088343Abstract: Apparatus including an array of memory cells and a controller configured to program all memory cells of a grouping of memory cells that are to be respectively programmed to different levels other than a lowest level, corresponding to a lowest data state, to an intermediate level from the lowest level, and to respectively program all the memory cells of the grouping of memory cells that are to be respectively programmed to the different levels other than the lowest level to the different levels other than the lowest level from the intermediate level.Type: ApplicationFiled: November 12, 2018Publication date: March 21, 2019Applicant: MICRON TECHNOLOGY, INC.Inventors: Carmine Miccoli, Christian Caillat, Akira Goda
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Patent number: 10153049Abstract: A method includes applying erase voltages to data lines and source lines of a memory block of memory cells in a non-volatile NAND architecture memory device during an erase operation. The memory block of memory cells includes a plurality of memory segments and a corresponding plurality of first select gate control lines. Each memory segment includes a plurality of memory sub-blocks that share a respective one of the first select gate control lines. The method includes applying a first bias voltage to the respective first select gate control line of a first one of the memory segments that has failed an erase verify operation to facilitate erasing the first memory segment during the erase operation, and applying a second bias voltage different from the first bias voltage to the respective first select gate control line of a second one of the memory segments that has passed the erase verify operation to facilitate inhibiting erasing of the second memory segment during the erase operation.Type: GrantFiled: October 2, 2017Date of Patent: December 11, 2018Assignee: Micron Technology, Inc.Inventors: Christian Caillat, Akira Goda
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Patent number: 10147494Abstract: Apparatus including an array of memory cells and a controller configured to apply a particular programming pulse to a plurality of memory cells having a first subset of memory cells having respective desired data states that are lower than a particular data state and a second subset of memory cells having respective desired data states that are higher than or equal to the particular data state, to at least partially inhibit each memory cell of the first subset of memory cells from programming while not inhibiting any memory cell of the second subset of memory cells from programming and while applying the particular programming pulse, then to apply a subsequent programming pulse while not inhibiting any memory cell of the first subset of memory cells from programming other than any memory cell of the first subset of memory cells having its respective desired data state equal to a lowest data state, and while not inhibiting any memory cell of the second subset of memory cells from programming.Type: GrantFiled: March 23, 2018Date of Patent: December 4, 2018Assignee: Micron Technology, Inc.Inventors: Carmine Miccoli, Christian Caillat, Akira Goda
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Publication number: 20180211714Abstract: Apparatus including an array of memory cells and a controller configured to apply a particular programming pulse to a plurality of memory cells having a first subset of memory cells having respective desired data states that are lower than a particular data state and a second subset of memory cells having respective desired data states that are higher than or equal to the particular data state, to at least partially inhibit each memory cell of the first subset of memory cells from programming while not inhibiting any memory cell of the second subset of memory cells from programming and while applying the particular programming pulse, then to apply a subsequent programming pulse while not inhibiting any memory cell of the first subset of memory cells from programming other than any memory cell of the first subset of memory cells having its respective desired data state equal to a lowest data state, and while not inhibiting any memory cell of the second subset of memory cells from programming.Type: ApplicationFiled: March 23, 2018Publication date: July 26, 2018Applicant: MICRON TECHNOLOGY, INC.Inventors: Carmine Miccoli, Christian Caillat, Akira Goda
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Patent number: 9953718Abstract: First memory cells are programmed to an intermediate level from a lowest level, corresponding to a lowest data state, where the first memory cells are to be programmed from the intermediate level to levels other than the lowest level. The first memory cells are not read or verified at the intermediate level. Different first memory cells of the first memory cells that are programmed to the intermediate level are respectively programmed to different levels of the levels other than the lowest level from the intermediate level. A second memory cell is programmed to a lower level than the different levels of the levels other than the lowest level from the lowest level while the different first memory cells are respectively programmed to the different levels of the levels other than the lowest level from the intermediate level.Type: GrantFiled: February 21, 2017Date of Patent: April 24, 2018Assignee: Micron Technology, Inc.Inventors: Carmine Miccoli, Christian Caillat, Akira Goda
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Publication number: 20180068737Abstract: A method includes applying erase voltages to data lines and source lines of a memory block of memory cells in a non-volatile NAND architecture memory device during an erase operation. The memory block of memory cells includes a plurality of memory segments and a corresponding plurality of first select gate control lines. Each memory segment includes a plurality of memory sub-blocks that share a respective one of the first select gate control lines. The method includes applying a first bias voltage to the respective first select gate control line of a first one of the memory segments that has failed an erase verify operation to facilitate erasing the first memory segment during the erase operation, and applying a second bias voltage different from the first bias voltage to the respective first select gate control line of a second one of the memory segments that has passed the erase verify operation to facilitate inhibiting erasing of the second memory segment during the erase operation.Type: ApplicationFiled: October 2, 2017Publication date: March 8, 2018Applicant: MICRON TECHNOLOGY, INC.Inventors: Christian Caillat, Akira Goda
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Patent number: 9779829Abstract: A method includes applying erase voltages to data lines and source lines of a memory block of memory cells in a non-volatile NAND architecture memory device during an erase operation. The memory block of memory cells includes a plurality of memory segments and a corresponding plurality of first select gate control lines. Each memory segment includes a plurality of memory sub-blocks that share a respective one of the first select gate control lines. The method includes applying a first bias voltage to the respective first select gate control line of a first one of the memory segments that has failed an erase verify operation to facilitate erasing the first memory segment during the erase operation, and applying a second bias voltage different from the first bias voltage to the respective first select gate control line of a second one of the memory segments that has passed the erase verify operation to facilitate inhibiting erasing of the second memory segment during the erase operation.Type: GrantFiled: November 17, 2015Date of Patent: October 3, 2017Assignee: Micron Technology, Inc.Inventors: Christian Caillat, Akira Goda
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Publication number: 20170178737Abstract: First memory cells are programmed to an intermediate level from a lowest level, corresponding to a lowest data state, where the first memory cells are to be programmed from the intermediate level to levels other than the lowest level. The first memory cells are not read or verified at the intermediate level. Different first memory cells of the first memory cells that are programmed to the intermediate level are respectively programmed to different levels of the levels other than the lowest level from the intermediate level. A second memory cell is programmed to a lower level than the different levels of the levels other than the lowest level from the lowest level while the different first memory cells are respectively programmed to the different levels of the levels other than the lowest level from the intermediate level.Type: ApplicationFiled: February 21, 2017Publication date: June 22, 2017Applicant: MICRON TECHNOLOGY, INC.Inventors: Carmine Miccoli, Christian Caillat, Akira Goda
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Publication number: 20170140833Abstract: A method includes applying erase voltages to data lines and source lines of a memory block of memory cells in a non-volatile NAND architecture memory device during an erase operation. The memory block of memory cells includes a plurality of memory segments and a corresponding plurality of first select gate control lines. Each memory segment includes a plurality of memory sub-blocks that share a respective one of the first select gate control lines. The method includes applying a first bias voltage to the respective first select gate control line of a first one of the memory segments that has failed an erase verify operation to facilitate erasing the first memory segment during the erase operation, and applying a second bias voltage different from the first bias voltage to the respective first select gate control line of a second one of the memory segments that has passed the erase verify operation to facilitate inhibiting erasing of the second memory segment during the erase operation.Type: ApplicationFiled: November 17, 2015Publication date: May 18, 2017Applicant: MICRON TECHNOLOGY, INC.Inventors: Christian Caillat, Akira Goda
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Patent number: 9633719Abstract: Embodiments of methods and memory devices for performing the methods are disclosed. In an embodiment, one such method includes programming all memory cells that are to be respectively programmed to different levels other than a lowest level, corresponding to a lowest data state, to an intermediate level from the lowest level and respectively programming all the memory cells that are to be respectively programmed to the different levels other than the lowest level to the different levels other than the lowest level from the intermediate level.Type: GrantFiled: May 29, 2015Date of Patent: April 25, 2017Assignee: Micron Technology, Inc.Inventors: Carmine Miccoli, Christian Caillat, Akira Goda
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Publication number: 20160351253Abstract: Embodiments of methods and memory devices for performing the methods are disclosed. In an embodiment, one such method includes programming all memory cells that are to be respectively programmed to different levels other than a lowest level, corresponding to a lowest data state, to an intermediate level from the lowest level and respectively programming all the memory cells that are to be respectively programmed to the different levels other than the lowest level to the different levels other than the lowest level from the intermediate level.Type: ApplicationFiled: May 29, 2015Publication date: December 1, 2016Applicant: MICRON TECHNOLOGY, INC.Inventors: Carmine Miccoli, Christian Caillat, Akira Goda
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Patent number: 9245759Abstract: A method of manufacturing a dual work function semiconductor device is disclosed. In one aspect, the method includes providing a substrate having first and second areas for forming first and second transistor types. The method additionally includes forming a dielectric layer on the substrate, which extends to cover at least parts of the first and second areas. The method additionally includes forming a first metal layer/stack on the dielectric layer in the first area, where the first metal layer/stack comprises a first work function-shifting element. The method additionally includes forming a second metal layer/stack on the first metal layer in the first area and on the dielectric layer in the second area, where the second metal layer/stack comprises a second work function-shifting element.Type: GrantFiled: October 7, 2013Date of Patent: January 26, 2016Assignee: IMECInventors: Tom Schram, Christian Caillat, Alessio Spessot, Pierre Fazan, Lars-Ake Ragnarsson, Romain Ritzenthaler
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Patent number: 9093311Abstract: Techniques for providing a semiconductor memory device are disclosed. In one embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region connected to a source line extending in a first orientation, a second region connected to a bit line extending a second orientation, and a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The semiconductor device may also include a first barrier wall extending in the first orientation of the array and a second barrier wall extending in the second orientation of the array and intersecting with the first barrier wall to form a trench region configured to accommodate each of the plurality of memory cells.Type: GrantFiled: June 9, 2014Date of Patent: July 28, 2015Assignee: Micron Technology, Inc.Inventors: Michael A. Van Buskirk, Christian Caillat, Viktor I. Koldiaev, Jungtae Kwon, Pierre C. Fazan