Abstract: A pseudo-random binary address generator is described which is designed for supplying addresses of cutting points of video signals for the purpose of encoding these signals by rotation of the two segments situated on either side of each cutting point, comprising three feedback registers (A), (B), (C) whose generating polynomials are irreducible and primitive, and in which the numbers of cells are different. These registers comprise several outputs a.sub.i b.sub.j c.sub.k, and the addresses of the cutting points are sums of N terms of weight 2.sup.O to 2.sup.N-1 and of coefficients S.sub.O to S.sub.N-1 of which at least a certain number are deduced from logic equations combining the outputs a.sub.i b.sub.j c.sub.k.

Abstract: An amplifier circuit comprising an amplifier (1) having an input (11) which receives an electric signal comprising an intermittent useful signal component V.sub.U and an undesired spurious component V.sub.D and an input (12) of opposite sign to that of the input (11). The output signal of a circuit (2) for the compensation of the spurious component is applied to amplifier input. The circuit (2) comprises a comparator (20) for comparing the undesired component, taken from the output of the amplifier (1), with a threshold value, a counter (21) which is incremented or decremented depending on the result of the comparisons and in the rhythm of a clock circuit (22), and a digital-to-analog converter (23) coupled to the output of the counter (21) to supply the signal for the compensation of the unwanted component to the input (12).

Abstract: System for digitizing and processing video signals incorporating a circuit (14) for separating the line synchronizing signals from an input video signal, a digital store for this input video signal, a write control circuit (18) for writing the input video signal into the store, a circuit (12) for processing the signals stored in the store and a read control circuit (22) for reading from the store and regaining an output video signal. This system includes a self-contained clock circuit formed by an oscillator (20) whose output signal is conveyed to the write control circuit (18), the read control circuit (22) and a delay counter (21), which gives the line synchronizing signal a delay which is equal to an integral number of times the line period, the output signal of the circuit (14) being conveyed to the read control circuit (22) after having passed through the counter (21).