Abstract: The disclosure relates to an amplifier comprising a digital delta-sigma modulator, a quantifier receiving a signal supplied by a delta-sigma stage and supplying a quantified signal, and a power circuit supplying an output signal. The device comprises N state loops of a first type configured to send the output signal to adders of N delta-sigma stages of lower rank, each state loop of the first type comprising an analog low-pass filter for supplying a filtered output signal, and an analog to digital converter for supplying a digital filtered output signal.

Abstract: The disclosure relates to an amplifier comprising a digital delta-sigma modulator, a quantifier receiving a signal supplied by a delta-sigma stage and supplying a quantified signal, and a power circuit supplying an output signal. The device comprises N state loops of a first type configured to send the output signal to adders of N delta-sigma stages of lower rank, each state loop of the first type comprising an analog low-pass filter for supplying a filtered output signal, and an analog to digital converter for supplying a digital filtered output signal.

Abstract: A process and an integrated circuit are intended for obtaining an adjustable electrical resistance, in which a first voltage is applied to an integrated MOS transistor on its source, its gate and its substrate, and a second voltage is applied on its drain, the first and second voltages being able to initiate a breakdown of the MOS transistor by: avalanche of the drain/substrate junction; biasing of the parasitic bipolar transistor of the MOS transistor; irreversible breakdown of the drain/substrate junction; and shorting between the drain and the source.