Abstract: A computer system is provided with a rack defining an interior. A computer chassis is mounted at least partially within the interior of the rack, wherein the computer chassis defines an interior. An interconnect assembly is mounted at least partially within the interior of the rack, wherein the interconnect assembly has an interconnect connector. A processor assembly is mounted at least partially within the interior of the computer chassis, and the processor assembly has a processor board and a processor connector mounted to the processor board and connected to the interconnect connector of the interconnect assembly. The processor assembly also has at least eight addressable processor segments mounted to the processor board.

Abstract: A method, system, and product for routing nets along a printed circuit board through an obstacle field and a circuit board having traces produced in accordance with the routed nets is disclosed. The nets are routed by identifying a general path for each of a pair of nets between adjacent rows of obstacles within an obstacle field, selectively lengthening at least one of the nets by shifting at least one portion of the net toward a position between adjacent pads in one of the rows, thereby increasing the length of the net, and selectively increasing the mean spacing between the pair of nets by shifting at least one portion of at least one net of the pair away from the other net of the pair toward a position between adjacent pads in one of the rows, thereby reducing cross-talk between the nets.

Abstract: A printed circuit board having a dielectric layer is disclosed. At least one signal trace is disposed adjacent a first surface of the dielectric layer in a first signal area. A reference plane is disposed adjacent a second surface of the dielectric layer in a first reference area positioned opposite the first signal area. The reference plane is configured to carry a reference potential for signals on the signal trace. At least one other signal trace is disposed adjacent the second surface of the dielectric layer in a second signal area and coupled to the signal trace in said first signal area. A second reference plane is disposed adjacent the first surface of the first dielectric layer in a second reference area positioned opposite the second signal area. The second reference plane is configured to carry the reference potential for signals on the other signal trace.

Abstract: An apparatus and method for positioning components on a circuit board and routing traces therebetween is disclosed. The circuit board has two pairs of electrical component-receiving footprint and a plurality of traces interconnecting the footprints. The two pairs of electrical component-receiving footprints are spaced from one another in a first direction, wherein the footprints in each of the pairs are substantially aligned in a second direction substantially perpendicular to the first direction, and wherein at least one of the footprints in one of the pairs is offset from at least one of the footprints in the other of the pairs in both the first and second directions. The plurality of traces interconnect each of the footprints includes at least one trace connecting the offset footprints.