Abstract: A mechanically stable main body having a cutout, into which an ESD protection element is at least partly embedded and mechanically fixed by means of a connection means. Electrical terminals of the protection element are connected to terminal pads on the top side of the main body by way of a structured metallic layer bearing on main body and protection element.

Abstract: A green film composed of varistor material laminated on a ceramic main body, which is provided with metallizations on both sides, and is sintered to form a varistor layer. A terminating electrode pair completes the arrangement and allows the varistor layer to be operated as a varistor. The upper second electrode pair can serve directly as a terminal contact for mounting an electrical component.

Abstract: A green film composed of varistor material is laminated on a ceramic main body (GK), which is provided with metallizations (EP1, AF) on both sides, and is sintered to form a varistor layer (VS). A terminating electrode pair (EP1, EP2) completes the arrangement and allows the varistor layer to be operated as a varistor. The upper second electrode pair (EP2) can serve directly as a terminal contact for mounting an electrical component.

Abstract: A mechanically stable main body having a cutout, into which an ESD protection element is at least partly embedded and mechanically fixed by means of a connection means. Electrical terminals of the protection element are connected to terminal pads on the top side of the main body by way of a structured metallic layer bearing on main body and protection element.

Abstract: A chip and a method for manufacturing a chip are disclosed. In an embodiment, the chip includes a varistor layer composed of zinc oxide, a multilayered electrode structure which realizes a varistor function in the varistor layer and at least two solderable or bondable external contacts on a first main surface of the varistor layer. The chip further includes a glass layer disposed on the first main surface leaving only the external contacts uncovered, wherein the glass layer includes, as main constituents, oxides of Si and/or Ge, B and K, which in total have at least 70% by weight of the constituents of the glass layer, and wherein the glass layer is substantially free of Al, Ga, Cr and Ti.

Abstract: A chip and a method for manufacturing a chip are disclosed. In an embodiment, the chip includes a varistor layer composed of zinc oxide, a multilayered electrode structure which realizes a varistor function in the varistor layer and at least two solderable or bondable external contacts on a first main surface of the varistor layer. The chip further includes a glass layer disposed on the first main surface leaving only the external contacts uncovered, wherein the glass layer includes, as main constituents, oxides of Si and/or Ge, B and K, which in total have at least 70% by weight of the constituents of the glass layer, and wherein the glass layer is substantially free of Al, Ga, Cr and Ti.

Abstract: A light-emitting diode device has a first carrier and at least one light-emitting diode chip, which is arranged on the first carrier. The first carrier has at least one first and one second carrier part, wherein the light-emitting diode chip rests only on the first carrier part. Furthermore, the first and second carrier parts each have a thermal conductivity. The thermal conductivity of the first carrier part is at least 1.5 times the thermal conductivity of the second carrier part. The first carrier part is surrounded laterally by the second carrier part.

Abstract: A light-emitting diode arrangement includes a light-emitting diode and a coding resistor for coding the light-emitting diode. The coding resistor is embodied as a star connection of a number of resistors. Furthermore, a module includes a plurality of light-emitting diode arrangements. Furthermore, a method for producing a light-emitting diode arrangement is specified, wherein the coding of a coding resistor is carried out depending on a determined characteristic of the light-emitting diode.

Abstract: A light-emitting diode arrangement includes a light-emitting diode and a coding resistor for coding the light-emitting diode. The coding resistor is embodied as a star connection of a number of resistors. Furthermore, a module includes a plurality of light-emitting diode arrangements. Furthermore, a method for producing a light-emitting diode arrangement is specified, wherein the coding of a coding resistor is carried out depending on a determined characteristic of the light-emitting diode.

Abstract: A light-emitting diode device has a first carrier and at least one light-emitting diode chip, which is arranged on the first carrier. The first carrier has at least one first and one second carrier part, wherein the light-emitting diode chip rests only on the first carrier part. Furthermore, the first and second carrier parts each have a thermal conductivity. The thermal conductivity of the first carrier part is at least 1.5 times the thermal conductivity of the second carrier part. The first carrier part is surrounded laterally by the second carrier part.

Abstract: A method for patterning a layer stack with at least one ceramic layer includes providing the ceramic layer, which has at least one plated-through hole. An electrically conductive layer is applied above the ceramic layer, such that the electrically conductive layer is electrically coupled to the at least one plated-through hole. A further layer is deposited onto the electrically conductive layer in the region of the at least one plated-through hole, wherein the further layer includes nickel. The electrically conductive layer is removed outside the region of the at least one plated-through hole. A carrier device patterned in this way can be electrically and mechanically coupled to an electronic component.

Abstract: A method for patterning a layer stack with at least one ceramic layer includes providing the ceramic layer, which has at least one plated-through hole. An electrically conductive layer is applied above the ceramic layer, such that the electrically conductive layer is electrically coupled to the at least one plated-through hole. A further layer is deposited onto the electrically conductive layer in the region of the at least one plated-through hole, wherein the further layer includes nickel. The electrically conductive layer is removed outside the region of the at least one plated-through hole. A carrier device patterned in this way can be electrically and mechanically coupled to an electronic component.

Abstract: In a microwave ceramic filter having a ceramic base body with metallized bores and an exterior metallization that is closed all over with the exception of the end face, metallic structures in the form of metallized recesses in the end face are formed on the non-metallized end face. These can be inserted as coupling structures and decoupling structures. The capacitance can be simply adjusted via the depth of the recesses. The size and the position of the contact surfaces for these coupling structures can be independently created on an exterior surface of the ceramic body.

Abstract: The invention relates to a component arrangement in which an electric component (5) is lowered into an indentation (4) of a circuit board (1) and in which the electric component (5) is attached to an auxiliary circuit board (6), which is connected in turn to the circuit board (1). By lowering the electric component (5) in the indentation (4) of the circuit board (1), the component remainder (U) can be reduced advantageously.