Abstract: An LED driver is disclosed that drives LEDs connected in parallel. Instead of applying current to all the parallel-connected LEDs at the same time, under control of a common PWM brightness control signal, the application of current to each parallel path is staggered by using staggered brightness control signals. The turning on of the LEDs in the different parallel paths will have the same duty cycle but will be out of phase. This reduces ripple in the power supply by reducing the magnitude of the instantaneous current sink. In one embodiment, a shift register contains a binary representation of the PWM duty cycle, and a clock shifts the bits along the shift register. The PWM brightness control signals for each parallel path of LEDs are tapped from different positions along the shift register so that the PWM brightness control signals are identical but staggered.

Abstract: An LED driver is disclosed that drives LEDs connected in parallel. Instead of applying current to all the parallel-connected LEDs at the same time, under control of a common PWM brightness control signal, the application of current to each parallel path is staggered by using staggered brightness control signals. The turning on of the LEDs in the different parallel paths will have the same duty cycle but will be out of phase. This reduces ripple in the power supply by reducing the magnitude of the instantaneous current sink. In one embodiment, a shift register contains a binary representation of the PWM duty cycle, and a clock shifts the bits along the shift register. The PWM brightness control signals for each parallel path of LEDs are tapped from different positions along the shift register so that the PWM brightness control signals are identical but staggered.

Abstract: An LED driver IC is described that uses a single pin to both set the maximum current through one or more driven LEDs and variably control the brightness of the LEDs. A single resistor is connected to the control pin of the IC, where the value of the resistor sets the maximum current through the LEDs. A PWM source, outputting a pulse train at a particular duty cycle, is connected to the other end of the resistor, where the duty cycle controls the LED brightness level. When the PWM signal is low (e.g. ground), a sample and hold circuit connects the output of a feedback control voltage to an Imax current source to set a maximum current based on the external resistor value. An inverse of the duty cycle of the PWM controller controls a current Idim that is subtracted from the maximum current Imax set by the resistor. This difference current is used to control drivers for the LEDs.

Abstract: An LED driver IC is described that uses a single pin to both set the maximum current through one or more driven LEDs and variably control the brightness of the LEDs. A single resistor is connected to the control pin of the IC, where the value of the resistor sets the maximum current through the LEDs. A PWM source, outputting a pulse train at a particular duty cycle, is connected to the other end of the resistor, where the duty cycle controls the LED brightness level. When the PWM signal is low (e.g. ground), a sample and hold circuit connects the output of a feedback control voltage to an Imax current source to set a maximum current based on the external resistor value. An inverse of the duty cycle of the PWM controller controls a current Idim that is subtracted from the maximum current Imax set by the resistor. This difference current is used to control drivers for the LEDs.

Abstract: An integrated circuit RF receiver processes multiple RF frequencies without internally changing the local oscillator to receive the multiple signals. No front-end tuner is used. In one embodiment, multiple crystals are connected to pins of the IC. A switch within the IC, controlled by a switch signal, selects one of the crystals as a reference frequency, depending on the frequency of the RF signal desired to be received. The selected reference frequency is applied to an RF synthesizer (a local oscillator) to set the output frequency of the RF synthesizer. The local oscillator signal is then mixed with the incoming RF signal to generate sum and difference signals that need to be filtered by an IF filter. The switch signal also reconfigures the IF filter to change its center frequency and filter bandwidth, based on the requirements of the RF signal data format.

Abstract: A data communication method for receiving digital data on a data terminal includes receiving data pulses having a first pulse separation to represent a first logical data value and a second pulse separation to represent a second logical data value, generating a voltage ramp signal, resetting the voltage ramp signal at a first delay after the leading edge of each data pulse, regenerating the voltage ramp signal at a first time period after the resetting of the voltage ramp signal, detecting the voltage value of the voltage ramp signal at the leading edge of each data pulse, and generating a data output signal associated with each data pulse. The data output signal has a first logical state when the voltage value of the voltage ramp signal is less than a threshold value and a second logical state when the voltage value of the voltage ramp signal is greater than the threshold value.

Abstract: A data communication method for receiving digital data on a data terminal includes receiving data pulses having a first pulse separation to represent a first logical data value and a second pulse separation to represent a second logical data value, generating a voltage ramp signal, resetting the voltage ramp signal a first delay after the leading edge of each data pulse, regenerating the voltage ramp signal a first time period after the resetting of the voltage ramp signal, detecting the voltage value of the voltage ramp signal at the leading edge of each data pulse, and generating a data output signal associated with each data pulse. The data output signal has a first logical state when the voltage value of the voltage ramp signal is less than a threshold value and a second logical state when the voltage value of the voltage ramp signal is greater than the threshold value.

Abstract: A peak detector employs switched capacitor filtering to implement long time constant and variable attack and decay characteristics. In one embodiment, the peak detector includes a first switch, a rectifier, a first capacitor and a second switch in the attack path, and a third switch, a second capacitor and a fourth switch in the decay path. The peak detector further includes a third capacitor coupled to the attack and decay paths and having a capacitance greater than the capacitance of the first and second capacitors. In operation, the attack path is activated by alternately closing the first and second switches to sample the input signal and generate an output voltage at the third capacitor indicative of the peak voltage value of the input signal. The second circuit path is activated by alternately closing the third and fourth switches to decrease the output voltage at the third capacitor.

Abstract: In a first aspect, a lock indicator circuit is disclosed. The lock indicator comprises a first circuit for providing a first beat signal; and a second circuit for providing a second beat signal. A reference clock signal and a recovered clock signal are provided in a reversed manner to the first and second circuits. In a second aspect, a method for providing a lock indication of a circuit is disclosed. The method comprises the steps of providing a first and second beat signals; and utilizing the first and second beat signals to determine if a lock condition has occurred. A system and method in accordance with the present invention indicates a lock to the desired reference clock and provides an error or out of lock condition if the recovered frequency is at a harmonic or subharmonic of the reference frequency. This ability to avoid a false lock indication requires very little additional circuitry.

Abstract: In a first aspect, a lock indicator circuit is disclosed. The lock indicator comprises a first circuit for providing a first beat signal; and a second circuit for providing a second beat signal. A reference clock signal and a recovered clock signal are provided in a reversed manner to the first and second circuits. In a second aspect, a method for providing a lock indication of a circuit is disclosed. The method comprises the steps of providing a first and second beat signals; and utilizing the first and second beat signals to determine if a lock condition has occurred. A system and method in accordance with the present invention indicates a lock to the desired reference clock and provides an error or out of lock condition if the recovered frequency is at a harmonic or subharmonic of the reference frequency. This ability to avoid a false lock indication requires very little additional circuitry.