Patents by Inventor Christian George Emor

Christian George Emor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11967556
    Abstract: Methods for forming microelectronic devices include forming a staircase structure in a stack structure having a vertically alternating sequence of insulative and conductive materials arranged in tiers. Steps are at lateral ends of the tiers. Contact openings of different aspect ratios are formed in fill material adjacent the staircase structure, with some openings terminating in the fill material and others exposing portions of the conductive material of upper tiers of the stack structure. Additional conductive material is selectively formed on the exposed portions of the conductive material. The contact openings initially terminating in the fill material are extended to expose portions of the conductive material of lower elevations. Contacts are formed, with some extending to the additional conductive material and others extending to conductive material of the tiers of the lower elevations. Microelectronic devices and systems incorporating such staircase structures and contacts are also disclosed.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: April 23, 2024
    Inventors: Biow Hiem Ong, David A. Daycock, Chieh Hsien Quek, Chii Wean Calvin Chen, Christian George Emor, Wing Yu Lo
  • Patent number: 11791268
    Abstract: Described are methods for forming a tungsten conductive structure over a substrate, such as a semiconductor substrate. Described examples include forming a silicon-containing material, such as a doped silicon-containing material, over a supporting structure. The silicon-containing material is then subsequently converted to a tungsten seed material containing the dopant material. A tungsten fill material of lower resistance will then be formed over the tungsten seed material.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: October 17, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Jordan D. Greenlee, Christian George Emor, Travis Rampton, Everett Allen McTeer, Rita J. Klein
  • Publication number: 20220302032
    Abstract: A microelectronic device includes a first conductive structure, a barrier structure, a conductive liner structure, and a second conductive structure. The first conductive structure is within a first filled opening in a first dielectric structure. The barrier structure is within the first filled opening in the first dielectric structure and vertically overlies the first conductive structure. The conductive liner structure is on the barrier structure and is within a second filled opening in a second dielectric structure vertically overlying the first dielectric structure. The second conductive structure vertically overlies and is horizontally surrounded by the conductive liner structure within the second filled opening in the second dielectric structure. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.
    Type: Application
    Filed: June 10, 2022
    Publication date: September 22, 2022
    Inventors: Jordan D. Greenlee, Christian George Emor, Luca Fumagalli, John D. Hopkins, Rita J. Klein, Christopher W. Petz, Everett A. McTeer
  • Publication number: 20220230962
    Abstract: Described are methods for forming a tungsten conductive structure over a substrate, such as a semiconductor substrate. Described examples include forming a silicon-containing material, such as a doped silicon-containing material, over a supporting structure. The silicon-containing material is then subsequently converted to a tungsten seed material containing the dopant material. A tungsten fill material of lower resistance will then be formed over the tungsten seed material.
    Type: Application
    Filed: February 7, 2022
    Publication date: July 21, 2022
    Inventors: Jordan D. Greenlee, Christian George Emor, Travis Rampton, Everett Allen McTeer, Rita J. Klein
  • Patent number: 11393756
    Abstract: A microelectronic device includes a first conductive structure, a barrier structure, a conductive liner structure, and a second conductive structure. The first conductive structure is within a first filled opening in a first dielectric structure. The barrier structure is within the first filled opening in the first dielectric structure and vertically overlies the first conductive structure. The conductive liner structure is on the barrier structure and is within a second filled opening in a second dielectric structure vertically overlying the first dielectric structure. The second conductive structure vertically overlies and is horizontally surrounded by the conductive liner structure within the second filled opening in the second dielectric structure. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: July 19, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Jordan D. Greenlee, Christian George Emor, Luca Fumagalli, John D. Hopkins, Rita J. Klein, Christopher W. Petz, Everett A. McTeer
  • Publication number: 20220045007
    Abstract: Methods for forming microelectronic devices include forming a staircase structure in a stack structure having a vertically alternating sequence of insulative and conductive materials arranged in tiers. Steps are at lateral ends of the tiers. Contact openings of different aspect ratios are formed in fill material adjacent the staircase structure, with some openings terminating in the fill material and others exposing portions of the conductive material of upper tiers of the stack structure. Additional conductive material is selectively formed on the exposed portions of the conductive material. The contact openings initially terminating in the fill material are extended to expose portions of the conductive material of lower elevations. Contacts are formed, with some extending to the additional conductive material and others extending to conductive material of the tiers of the lower elevations. Microelectronic devices and systems incorporating such staircase structures and contacts are also disclosed.
    Type: Application
    Filed: October 25, 2021
    Publication date: February 10, 2022
    Inventors: Biow Hiem Ong, David A. Daycock, Chieh Hsien Quek, Chii Wean Calvin Chen, Christian George Emor, Wing Yu Lo
  • Patent number: 11244903
    Abstract: Described are methods for forming a tungsten conductive structure over a substrate, such as a semiconductor substrate. Described examples include forming a silicon-containing material, such as a doped silicon-containing material, over a supporting structure. The silicon-containing material is then subsequently converted to a tungsten seed material containing the dopant material. A tungsten fill material of lower resistance will then be formed over the tungsten seed material.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: February 8, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Jordan D. Greenlee, Christian George Emor, Travis Rampton, Everett Allen McTeer, Rita J. Klein
  • Patent number: 11158577
    Abstract: Methods for forming microelectronic devices include forming a staircase structure in a stack structure having a vertically alternating sequence of insulative and conductive materials arranged in tiers. Steps are at lateral ends of the tiers. Contact openings of different aspect ratios are formed in fill material adjacent the staircase structure, with some openings terminating in the fill material and others exposing portions of the conductive material of upper tiers of the stack structure. Additional conductive material is selectively formed on the exposed portions of the conductive material. The contact openings initially terminating in the fill material are extended to expose portions of the conductive material of lower elevations. Contacts are formed, with some extending to the additional conductive material and others extending to conductive material of the tiers of the lower elevations. Microelectronic devices and systems incorporating such staircase structures and contacts are also disclosed.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: October 26, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Biow Hiem Ong, David A. Daycock, Chieh Hsien Quek, Chii Wean Calvin Chen, Christian George Emor, Wing Yu Lo
  • Publication number: 20210287990
    Abstract: A microelectronic device comprises a first conductive structure, a barrier structure, a conductive liner structure, and a second conductive structure. The first conductive structure is within a first filled opening in a first dielectric structure. The barrier structure is within the first filled opening in the first dielectric structure and vertically overlies the first conductive structure. The conductive liner structure is on the barrier structure and is within a second filled opening in a second dielectric structure vertically overlying the first dielectric structure. The second conductive structure vertically overlies and is horizontally surrounded by the conductive liner structure within the second filled opening in the second dielectric structure. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.
    Type: Application
    Filed: March 16, 2020
    Publication date: September 16, 2021
    Inventors: Jordan D. Greenlee, Christian George Emor, Luca Fumagalli, John D. Hopkins, Rita J. Klein, Christopher W. Petz, Everett A. McTeer
  • Publication number: 20210242131
    Abstract: Methods for forming microelectronic devices include forming a staircase structure in a stack structure having a vertically alternating sequence of insulative and conductive materials arranged in tiers. Steps are at lateral ends of the tiers. Contact openings of different aspect ratios are formed in fill material adjacent the staircase structure, with some openings terminating in the fill material and others exposing portions of the conductive material of upper tiers of the stack structure. Additional conductive material is selectively formed on the exposed portions of the conductive material. The contact openings initially terminating in the fill material are extended to expose portions of the conductive material of lower elevations. Contacts are formed, with some extending to the additional conductive material and others extending to conductive material of the tiers of the lower elevations. Microelectronic devices and systems incorporating such staircase structures and contacts are also disclosed.
    Type: Application
    Filed: January 31, 2020
    Publication date: August 5, 2021
    Inventors: Biow Hiem Ong, David A. Daycock, Chieh Hsien Quek, Chii Wean Calvin Chen, Christian George Emor, Wing Yu Lo
  • Publication number: 20210202388
    Abstract: Described are methods for forming a tungsten conductive structure over a substrate, such as a semiconductor substrate. Described examples include forming a silicon-containing material, such as a doped silicon-containing material, over a supporting structure. The silicon-containing material is then subsequently converted to a tungsten seed material containing the dopant material. A tungsten fill material of lower resistance will then be formed over the tungsten seed material.
    Type: Application
    Filed: December 30, 2019
    Publication date: July 1, 2021
    Inventors: Jordan D. Greenlee, Christian George Emor, Travis Rampton, Everett Allen McTeer, Rita J. Klein