Abstract: Techniques for achieving the effects of significantly reducing the amount of computer memory needed to simulate the behavior of a multi-stage pipelined processor, as well as, significantly increasing the performance of the simulation process by eliminating the storing and copying of redundant information are described. These beneficial effects are achieved by reordering the chronological sequence of execution of software models of the various pipeline stages with respect to the actual instruction-flow sequence implemented by the processor hardware. This approach takes advantage of the independence of the stages within a cycle to make the results computed by a previous stage directly available to its subsequent stage without the use of transient data space or data copying. In particular, it is shown how to apply this technique to the simulation of a multi-parallel-stage VLIW array processor, such as the manifold array (ManArray) processor.

Abstract: A method of expanding an image stored in a first array including the steps of separating the first array into a plurality of rows, each row having a first plurality of data elements, each element having a value, and separately expanding each row from a first plurality of data elements in the first array to a second plurality of data elements in a second array including the steps of correlating each of the first plurality of data elements to at least one of the second plurality of data elements, and distributing the value of selected elements of the first plurality of data elements to correlated data elements of the second plurality of data elements.