Abstract: In certain aspects, a system includes a first filter, a second filter, a dummy load, and a switching circuit coupled to the first filter, the second filter, and the dummy load, and coupled to a first antenna and a second antenna. In a first mode, the switching circuit couples the first filter and the second filter to the first antenna, and, in a second mode, the switching circuit couples the first filter and the third filter to the first antenna and couples the second filter to the second antenna. In certain aspects, the dummy load includes a third filter.

Abstract: An apparatus includes a low noise amplifier (LNA) multiplexer configured to receive a plurality of radio frequency (RF) signals at a plurality of input terminals and to combine the plurality of RF signals into a combined RF signal that is output at an output terminal. The LNA multiplexer includes a plurality of input signal paths, and each input signal path is coupleable to a respective input terminal of the plurality of input terminals and is configured to receive a respective RF signal of the plurality of RF signals. The apparatus further includes an LNA demultiplexer configured to receive the combined RF signal at an input port coupled to the output terminal and to distribute the combined RF signal to a plurality of output ports, each output port of the plurality of output ports configured to output the combined RF signal to a respective downconverter of a plurality of downconverters.

Abstract: Techniques for using a narrow filter located before a power amplifier to reduce interference in an adjacent frequency band are disclosed. In an exemplary design, an apparatus (e.g., a wireless device) includes the narrow filter and the power amplifier. The narrow filter is for a first frequency band (e.g., Band 40) and has a first bandwidth that is more narrow than the first frequency band. The narrow filter receives and filters an input radio frequency (RF) signal and provides a filtered RF signal. The power amplifier receives and amplifies the filtered RF signal and provides an amplified RF signal. The apparatus may further include a full filter for the first frequency band and located after the power amplifier. The full filter receives and filters the amplified RF signal and provides an output RF signal when it is selected for use.

Abstract: The described apparatus and methods may include a receiver configured to receive a control signal, and a controller configured to regulate power consumption of the receiver during intervals of less than one radio frame based on the control signals. The controller may also be configured to regulate power consumption of a transmitter during intervals of less than one radio frame based on the control signal.

Abstract: An apparatus includes a low noise amplifier (LNA) multiplexer configured to receive a plurality of radio frequency (RF) signals at a plurality of input terminals and to combine the plurality of RF signals into a combined RF signal that is output at an output terminal. The LNA multiplexer includes a plurality of input signal paths, and each input signal path is coupleable to a respective input terminal of the plurality of input terminals and is configured to receive a respective RF signal of the plurality of RF signals. The apparatus further includes an LNA demultiplexer configured to receive the combined RF signal at an input port coupled to the output terminal and to distribute the combined RF signal to a plurality of output ports, each output port of the plurality of output ports configured to output the combined RF signal to a respective downconverter of a plurality of downconverters.

Abstract: Multiplex modules for use in carrier aggregation receivers are disclosed. In an exemplary embodiment, an apparatus includes an LNA multiplexer configured to receive a plurality of RF signals at a plurality of input terminals and to combine the RF signals into a combined RF signal that is output from an output terminal. The apparatus also includes an LNA demultiplexer configured to receive the combined RF signal at an input port that is connected to the output terminal and to distribute the combined RF signal to a plurality of output ports.

Abstract: A wireless communication device configured for receiving a multiple carrier signal is described. The wireless communication device includes a single-chip signal splitting carrier aggregation receiver architecture. The single-chip signal splitting carrier aggregation receiver architecture includes a primary antenna, a secondary antenna and a transceiver chip. The single-chip signal splitting carrier aggregation receiver architecture reuses a simultaneous hybrid dual receiver path.

Abstract: Techniques for supporting data transmission and reception on multiple bands for carrier aggregation are disclosed. In an exemplary design, an apparatus (e.g., a wireless device) includes first and second antenna interface circuits coupled to first and second antennas, respectively. The first antenna interface circuit includes a first transmit (TX) filter for a first band, which may be part of a first triplexer or duplexer. The first TX filter filters a first radio frequency (RF) signal prior to transmission via the first antenna. The second antenna interface circuit includes a second TX filter for a second band, which may be part of a second triplexer or duplexer. The second TX filter filters a second RF signal prior to transmission via the second antenna. The first and second RF signals may be transmitted simultaneously on the first and second bands for carrier aggregation.

Abstract: A receiver architecture for carrier aggregation is disclosed. In an exemplary design, an apparatus (e.g., a wireless device, a circuit module, etc.) includes a plurality of low noise amplifiers (LNAs), a plurality of switches, and at least one downconverter. The LNAs receive and amplify at least one input radio frequency (RF) signal and provide at least one amplified RF signal. The switches are coupled to the outputs of the plurality of LNAs. The at least one downconverter is coupled to the plurality of switches, downconverts the at least one amplified RF signal, and provides at least one downconverted signal. The switches reduce the number of downconverters needed to support reception of transmissions on multiple sets of carriers via multiple receive antennas. The LNAs and the switches may be implemented on at least one front-end module or a back-end module. The downconverter(s) are implemented on the back-end module.

Abstract: Multiplex modules for use in carrier aggregation receivers are disclosed. In an exemplary embodiment, an apparatus includes an LNA multiplexer configured to receive a plurality of RF signals at a plurality of input terminals and to combine the RF signals into a combined RF signal that is output from an output terminal The apparatus also includes an LNA demultiplexer configured to receive the combined RF signal at an input port that is connected to the output terminal and to distribute the combined RF signal to a plurality of output ports.

Abstract: A radio frequency package on package (PoP) circuit is described. The radio frequency package on package (PoP) circuit includes a first radio frequency package. The first radio frequency package includes radio frequency components. The radio frequency package on package (PoP) circuit also includes a second radio frequency package. The second radio frequency package includes radio frequency components. The first radio frequency package and the second radio frequency package are in a vertical configuration. The radio frequency components on the first radio frequency package are designed to reduce the effects of ground inductance.

Abstract: Amplifiers with multiple outputs and separate gain control per output are disclosed. In an exemplary design, an apparatus (e.g., a wireless device or an integrated circuit) may include first and second amplifier circuits. The first amplifier circuit may receive and amplify an input radio frequency (RF) signal based on a first variable gain and provide a first amplified RF signal. The second amplifier circuit may receive and amplify the input RF signal based on a second variable gain and provide a second amplified RF signal. The input RF signal may include a plurality of transmitted signals being received by the wireless device. The first variable gain may be adjustable independently of the second variable gain. Each variable gain may be set based on the received power level of at least one transmitted signal being received by the wireless device.

Abstract: The described apparatus and methods may include a receiver configured to receive a control signal, and a controller configured to regulate power consumption of the receiver during intervals of less than one radio frame based on the control signals. The controller may also be configured to regulate power consumption of a transmitter during intervals of less than one radio frame based on the control signal.

Abstract: The described apparatus and methods may include a receiver configured to receive a control signal, and a controller configured to regulate power consumption of the receiver during intervals of less than one radio frame based on the control signals. The controller may also be configured to regulate power consumption of a transmitter during intervals of less than one radio frame based on the control signal.

Abstract: Amplifiers with multiple outputs and separate gain control per output are disclosed. In an exemplary design, an apparatus (e.g., a wireless device or an integrated circuit) may include first and second amplifier circuits. The first amplifier circuit may receive and amplify an input radio frequency (RF) signal based on a first variable gain and provide a first amplified RF signal. The second amplifier circuit may receive and amplify the input RF signal based on a second variable gain and provide a second amplified RF signal. The input RF signal may include a plurality of transmitted signals being received by the wireless device. The first variable gain may be adjustable independently of the second variable gain. Each variable gain may be set based on the received power level of at least one transmitted signal being received by the wireless device.

Abstract: A receiver architecture for carrier aggregation is disclosed. In an exemplary design, an apparatus (e.g., a wireless device, a circuit module, etc.) includes a plurality of low noise amplifiers (LNAs), a plurality of switches, and at least one downconverter. The LNAs receive and amplify at least one input radio frequency (RF) signal and provide at least one amplified RF signal. The switches are coupled to the outputs of the plurality of LNAs. The at least one downconverter is coupled to the plurality of switches, downconverts the at least one amplified RF signal, and provides at least one downconverted signal. The switches reduce the number of downconverters needed to support reception of transmissions on multiple sets of carriers via multiple receive antennas. The LNAs and the switches may be implemented on at least one front-end module or a back-end module. The downconverter(s) are implemented on the back-end module.

Abstract: A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.

Abstract: A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.

Abstract: Techniques for supporting data transmission and reception on multiple bands for carrier aggregation are disclosed. In an exemplary design, an apparatus (e.g., a wireless device) includes first and second antenna interface circuits coupled to first and second antennas, respectively. The first antenna interface circuit includes a first transmit (TX) filter for a first band, which may be part of a first triplexer or duplexer. The first TX filter filters a first radio frequency (RF) signal prior to transmission via the first antenna. The second antenna interface circuit includes a second TX filter for a second band, which may be part of a second triplexer or duplexer. The second TX filter filters a second RF signal prior to transmission via the second antenna. The first and second RF signals may be transmitted simultaneously on the first and second bands for carrier aggregation.

Abstract: A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.