Abstract: To generate quickly the several carry signals in a full adder circuit (for example a 40-bit circuit), the circuit is divided into a plurality of sub-circuits of a first type, in which complementary imaginary carry signals are generated parallel to each other. Carry look-ahead circuits are of a dual construction, each first carry look-ahead circuit receiving a logic "0" and each second carry look-ahead circuit receiving a login "1". So the generated imaginary carry signals are complementary, from which the carry signal proper is selected with the aid of a multiplex switch. The multiplex switch is controlled by the carry signal generated in a preceding sub-circuit of the first type. Since a multiplex switch operates faster than 3-bit or 4-bit wide carry look-ahead circuits, which operate in parallel in groups, the carry signals are consequently generated faster.

Abstract: A data transmission system comprising a control unit, a transmitter and a receiver, the transmitter and receiver being connected by a transmission line for the serial transmission of a series of data words in a sequence of subsequent data bits. The control unit is provided with a word select signal generator for generating a two level word select signal for selecting, under control of a level change, a data word to be transmitted. The time length between two successive level changes of the word select signal is variable.

Abstract: An integrated data processor which includes a multiplier element provided with non-symmetrical operand inputs and an arithmetic and logic unit which is connected to the output of the multiplier element by way of a connection over the full product width. The ALU also comprises an accumulator device. Multiple-precision operations can thus be performed on the quantities received on each of the two inputs of the multiplier element. The data processor is notably suitable for performing each time identical operations on sequentially arriving signal quantities.