Abstract: Concurrent servicing of a first cable of a cable pair while a second cable of the cable pair remains operational improves multi-processor computer system availability and serviceability. A pair of processing chips in different processing drawers may continue operation by way of the second cable while the first cable is degraded or serviced. Upon the servicing of the first cable, the serviced cable may transition to a fully operational state with no interruptions to the operations between the processing drawers by way of the second cable. Since cable faults are typically more common than processing chip or processing drawer faults, identification of cable faults and the ability to maintain operations of the processing drawers connected therewith is increasingly important.

Abstract: Embodiments include in response to monitoring a processor during operation, detecting a first number of core recovery events in the processor, determining that the first number of core recovery events fulfills a first condition for the first core recovery events threshold, and modifying a value of at least one droop sensor parameter of the processor by a first amount. The at least one droop sensor parameters affects a sensitivity to a voltage droop. In response to modifying the value of the droop sensor parameter by the first amount, a second number of core recovery events is detected in the processor. It is determined that the second number of core recovery events fulfills a second condition for a second core recovery events threshold, and the value of the at least one droop sensor parameter is modified by a second amount.

Abstract: Aspects include using a shadow copy of a level 1 (L1) cache in a cache hierarchy. A method includes maintaining the shadow copy of the L1 cache in the cache hierarchy. The maintaining includes updating the shadow copy of the L1 cache with memory content changes to the L1 cache a number of pipeline cycles after the L1 cache is updated with the memory content changes.

Abstract: Embodiments of the invention are directed to a computer-implemented method of operating a data transmission system. The data transmission system includes a transmitter and a receiver. The computer-implemented method includes using the transmitter to send serialized data from the transmitter through a plurality of lanes to the receiver. The transmitter sends the serialized data at a first serialization ratio. The receiver is configured to receive and load the serialized data at a second deserialization ratio, wherein the first serialization ration is greater than the second deserialization ratio.

Abstract: A computer-implemented method is provided. The method includes determining whether a rejection of a request is required and determining whether the request is software forward progress (SFP)-likely or SFP-unlikely upon determining that the rejection of the request is required. The method also includes executing a first pseudo random decision to set or not set a requested state of the request in an event the request is SFP-likely or SFP-unlikely, respectively, and rejecting the request following execution of the second pseudo random decision.

Abstract: A method and a system detects a cache line as a potential or confirmed hot cache line based on receiving an intervention of a processor associated with a fetch of the cache line. The method and system include suppressing an action of operations associated with the hot cache line. A related method and system detect an intervention and, in response, communicates an intervention notification to another processor. An alternative method and system detect a hot data object associated with an intervention event of an application. The method and system can suppress actions of operations associated with the hot data object. An alternative method and system can detect and communicate an intervention associated with a data object.

Abstract: Embodiments include in response to monitoring a processor during operation, detecting a first number of core recovery events in the processor, determining that the first number of core recovery events fulfills a first condition for the first core recovery events threshold, and modifying a value of at least one droop sensor parameter of the processor by a first amount. The at least one droop sensor parameters affects a sensitivity to a voltage droop. In response to modifying the value of the droop sensor parameter by the first amount, a second number of core recovery events is detected in the processor. It is determined that the second number of core recovery events fulfills a second condition for a second core recovery events threshold, and the value of the at least one droop sensor parameter is modified by a second amount.

Abstract: Embodiments include in response to monitoring a processor during operation, detecting a first number of throttling amounts in the processor, determining that the first number of throttling amounts fulfills a first condition regarding a throttling amounts threshold, and modifying a voltage level of the processor by a first amount. Embodiments include in response to modifying the voltage level of the processor by the first amount, detecting a second number of throttling amounts in the processor, determining that the second number of throttling amounts fulfills a second condition regarding the throttling amounts threshold, and modifying the voltage level of the processor by a second amount.

Abstract: Disclosed herein is a virtual cache and method in a processor for supporting multiple threads on the same cache line. The processor is configured to support virtual memory and multiple threads. The virtual cache directory includes a plurality of directory entries, each entry is associated with a cache line. Each cache line has a corresponding tag. The tag includes a logical address, an address space identifier, a real address bit indicator, and a per thread validity bit for each thread that accesses the cache line. When a subsequent thread determines that the cache line is valid for that thread the validity bit for that thread is set, while not invalidating any validity bits for other threads.

Abstract: Concurrent servicing of a first cable of a cable pair while a second cable of the cable pair remains operational improves multi-processor computer system availability and serviceability. A pair of processing chips in different processing drawers may continue operation by way of the second cable while the first cable is degraded or serviced. Upon the servicing of the first cable, the serviced cable may transition to a fully operational state with no interruptions to the operations between the processing drawers by way of the second cable. Since cable faults are typically more common than processing chip or processing drawer faults, identification of cable faults and the ability to maintain operations of the processing drawers connected therewith is increasingly important.

Abstract: The method and systems described herein provide for identifying and mitigating undesirable power or voltage fluctuations in regions of a semiconductor device. For example, embodiments include detecting a region, such as an individual processor, of a processor chip is exhibiting a reduced power draw and a resulting localized voltage spike (e.g., a spike that exceeds Vmax) that would accelerate overall device end-of-life (EOL). The described systems respond by activating circuits or current generators located in the given region to draw additional power via a protective current. The protective current lowers the local voltages spikes back to within some pre-specified range (e.g., below a Vmax). The resulting reduction in the time above Vmax in testing reduces the number of devices that will need to be discarded due to Vmax violations as well as increases the expected reliability and lifespan of the device in operation.

Abstract: A primary controller has authority of a cache line associated with a fetch and manages a second cache line request from a different and non-associated secondary requesting entity. A secondary controller, associated with the secondary requesting entity, is granted authority of the cache line and further manages multiple subsequent simultaneous or overlapping requests for the cache line from different non-associated subsequent requesting entities by maintaining authority of the cache line, by granting read-only access to the cache line to respective subsequent controllers, each associated with a different subsequent requesting entity, and by passing a non-authority token to each of the respective subsequent controllers.

Abstract: A computer-implemented method is provided. The method includes determining whether a rejection of a request is required and determining whether the request is software forward progress (SFP)-likely or SFP-unlikely upon determining that the rejection of the request is required. The method also includes executing a first pseudo random decision to set or not set a requested state of the request in an event the request is SFP-likely or SFP-unlikely, respectively, and rejecting the request following execution of the second pseudo random decision.

Abstract: The method and systems described herein provide for identifying and mitigating undesirable power or voltage fluctuations in regions of a semiconductor device. For example, embodiments include detecting a region, such as an individual processor, of a processor chip is exhibiting a reduced power draw and a resulting localized voltage spike (e.g., a spike that exceeds Vmax) that would accelerate overall device end-of-life (EOL). The described systems respond by activating circuits or current generators located in the given region to draw additional power via a protective current. The protective current lowers the local voltages spikes back to within some pre-specified range (e.g., below a Vmax). The resulting reduction in the time above Vmax in testing reduces the number of devices that will need to be discarded due to Vmax violations as well as increases the expected reliability and lifespan of the device in operation.

Abstract: Aspects include using a shadow copy of a level 1 (L1) cache in a cache hierarchy. A method includes maintaining the shadow copy of the L1 cache in the cache hierarchy. The maintaining includes updating the shadow copy of the L1 cache with memory content changes to the L1 cache a number of pipeline cycles after the L1 cache is updated with the memory content changes.

Abstract: Embodiments are for using a decentralized hot cache line tracking fairness mechanism. In response to receiving an incoming request to access a cache line, a determination is made to grant access to the cache line based on a requested state and a serviced state used for maintaining the cache line, a structure comprising the requested and serviced states. In response to the determination to grant access to the cache line, the requested state and the serviced state are transferred along with data of the cache line.

Abstract: A computer system includes a processor core and a memory system in signal communication with the processor core. The memory system includes a first cache and a second cache. The first cache is arranged at a first level of a hierarchy in the memory system and is configured to store a plurality of first-cache entries. The second cache is arranged at a second level of the hierarchy that is lower than the first level, and stores a plurality of second-cache entries. The first cache maintains a directory that contains information for each of the first-cache entries. The second cache maintains a shadow pointer directory (SPD) that includes one or more SPD entries that maps each of the first-cache entries to a corresponding second cache entry at a lower-level cache location.

Abstract: A primary controller has authority of a cache line associated with a fetch and manages a second cache line request from a different and non-associated secondary requesting entity. A secondary controller, associated with the secondary requesting entity, is granted authority of the cache line and further manages multiple subsequent simultaneous or overlapping requests for the cache line from different non-associated subsequent requesting entities by maintaining authority of the cache line, by granting read-only access to the cache line to respective subsequent controllers, each associated with a different subsequent requesting entity, and by passing a non-authority token to each of the respective subsequent controllers.

Abstract: Disclosed herein is a virtual cache and method in a processor for supporting multiple threads on the same cache line. The processor is configured to support virtual memory and multiple threads. The virtual cache directory includes a plurality of directory entries, each entry is associated with a cache line. Each cache line has a corresponding tag. The tag includes a logical address, an address space identifier, a real address bit indicator, and a per thread validity bit for each thread that accesses the cache line. When a subsequent thread determines that the cache line is valid for that thread the validity bit for that thread is set, while not invalidating any validity bits for other threads.

Abstract: An input/output store instruction is handled. A data processing system includes a system nest communicatively coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is communicatively coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to an external device which is communicatively coupled to the input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed.