Patents by Inventor Christian Jacobi

Christian Jacobi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Sort and merge instruction for a general-purpose processor
    Patent number: 10831478
    Abstract: A Sort Lists instruction is provided to perform a sort and/or a merge operation. The instruction is an architected machine instruction of an instruction set architecture and is executed by a general-purpose processor of the computing environment. The executing includes sorting a plurality of input lists to obtain one or more sorted output lists, which are output.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce C. Giamei, Martin Recktenwald, Donald W. Schmidt, Timothy Slegel, Aditya N. Puranik, Mark S. Farrell, Christian Jacobi, Jonathan D. Bradbury, Christian Zoellin
  • Migration of partially completed instructions
    Patent number: 10831502
    Abstract: Migration of partially completed instructions. A determination is made that processing of an operation of an instruction executing on a processor has been interrupted prior to completion. The instruction is re-executed on a selected processor to resume forward processing of the instruction. The re-executing includes determining whether model-dependent metadata is to be used by the selected processor in re-executing the instruction. Based on determining the model-dependent metadata is to be used, the model-dependent metadata is used in re-executing the instruction. Based on determining the model-dependent metadata is not to be used, proceeding with re-executing the instruction without using the model-dependent metadata.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce C. Giamei, Martin Recktenwald, Donald W. Schmidt, Timothy Slegel, Aditya N. Puranik, Mark S. Farrell, Christian Jacobi, Jonathan D. Bradbury, Christian Zoellin
  • Compression/decompression instruction specifying a history buffer to be used in the compression/decompression of data
    Patent number: 10831497
    Abstract: An instruction to perform a function of a plurality of functions is obtained. The instruction is a single architected instruction of an instruction set architecture that complies to an industry standard for compression. The instruction is executed, and the executing includes performing the function specified by the instruction. The performing includes, based on the function being a compression function or a decompression function, transforming state of input data between an uncompressed form of the input data and a compressed form of the input data to provide a transformed state of data accessing. During performing the function, history relating to the function is accessed. The history is to be used in transforming the state of input data between the uncompressed form and the compressed form.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce C. Giamei, Anthony T. Sofia, Matthias Klein, Simon Weishaupt, Mark S. Farrell, Timothy Slegel, Ashutosh Mishra, Christian Jacobi
  • Saving and restoring machine state between multiple executions of an instruction
    Patent number: 10831503
    Abstract: Saving and restoring machine state between multiple executions of an instruction. A determination is made that processing of an operation of an instruction executing on a processor has been interrupted prior to completion. Based on determining that the processing of the operation has been interrupted, current metadata of the processor is extracted. The metadata is stored in a location associated with the instruction and used to re-execute the instruction to resume forward processing of the instruction from where it was interrupted.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce C. Giamei, Martin Recktenwald, Donald W. Schmidt, Timothy Slegel, Aditya N. Puranik, Mark S. Farrell, Christian Jacobi, Jonathan D. Bradbury, Christian Zoellin
  • Translation support for a virtual cache
    Patent number: 10831674
    Abstract: Disclosed herein is a virtual cache and method in a processor for supporting multiple threads on the same cache line. The processor is configured to support virtual memory and multiple threads. The virtual cache directory includes a plurality of directory entries, each entry is associated with a cache line. Each cache line has a corresponding tag. The tag includes a logical address, an address space identifier, a real address bit indicator, and a per thread validity bit for each thread that accesses the cache line. When a subsequent thread determines that the cache line is valid for that thread the validity bit for that thread is set, while not invalidating any validity bits for other threads.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Markus Helms, Christian Jacobi, Ulrich Mayer, Martin Recktenwald, Johannes C. Reichart, Anthony Saporito, Aaron Tsai
  • SAVING AND RESTORING MACHINE STATE BETWEEN MULTIPLE EXECUTIONS OF AN INSTRUCTION
    Publication number: 20200348940
    Abstract: Saving and restoring machine state between multiple executions of an instruction. A determination is made that processing of an operation of an instruction executing on a processor has been interrupted prior to completion. Based on determining that the processing of the operation has been interrupted, current metadata of the processor is extracted. The metadata is stored in a location associated with the instruction and used to re-execute the instruction to resume forward processing of the instruction from where it was interrupted.
    Type: Application
    Filed: July 20, 2020
    Publication date: November 5, 2020
    Inventors: Bruce C. Giamei, Martin Recktenwald, Donald W. Schmidt, Timothy Slegel, Aditya N. Puranik, Mark S. Farrell, Christian Jacobi, Jonathan D. Bradbury, Christian Zoellin
  • Generating and verifying hardware instruction traces including memory data contents
    Patent number: 10824426
    Abstract: Embodiments of the present invention are directed to a computer-implemented method for generating and verifying hardware instruction traces including memory data contents. The method includes initiating an in-memory trace (IMT) data capture for a processor, the IMT data being an instruction trace collected while instructions flow through an execution pipeline of the processor. The method further includes capturing contents of architected registers of the processor by: storing the contents of the architected registers to a predetermined memory location, and causing a load-store unit (LSU) to read contents of the predetermined memory location.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: November 3, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jane H. Bartik, Christian Jacobi, David Lee, Jang-Soo Lee, Anthony Saporito, Christian Zoellin
  • High efficiency redundant array of independent memory
    Patent number: 10824508
    Abstract: A memory system includes memory modules having a number of sets of memory devices including data memory devices for data and error correction code (ECC). The ECC memory devices carry ECC symbols for the memory modules. A host receives and decodes the ECC symbols and executes error correction operations. The host and the memory modules are coupled by a number of channels.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: November 3, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Patrick J. Meaney, Christian Jacobi, Barry M. Trager
  • Sharing virtual and real translations in a virtual cache
    Patent number: 10810134
    Abstract: Disclosed herein is a virtual cache directory in a processor that eliminates address translations when the virtual address and the real address in the cache directory are the same. The processor is configured to support virtual memory and multiple threads. The virtual cache directory includes a plurality of directory entries, each entry is associated with a cache line. Each cache line has a tag. The tag includes a logical address, an address space identifier, a real address bit indicator, and virtual address to real address indicator. This virtual address to real address indicator indicates if the logical address and the real address are the same. When activated, address translation is not performed.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: October 20, 2020
    Assignee: International Business Machines Corporation
    Inventors: Markus Helms, Christian Jacobi, Martin Recktenwald, Johannes C. Reichart
  • Marking to indicate memory used to back address translation structures
    Patent number: 10802986
    Abstract: A marking capability is used to provide an indication of whether a block of memory is backing an address translation structure of a control program being managed by a virtual machine manager. By providing the marking, the virtual machine manager may check the indication prior to making paging decisions. With this information, a hint may be provided to the hardware to be used in decisions relating to purging associated address translation structures, such as translation look-aside buffer (TLB) entries.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: October 13, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonathan D. Bradbury, Lisa Cranton Heller, Christian Jacobi, Damian L. Osisek, Anthony Saporito
  • Speculative data return concurrent to an exclusive invalidate request
    Patent number: 10795824
    Abstract: Speculative data return in parallel with an exclusive invalidate request. A requesting processor requests data from a shared cache. The data is owned by another processor. Based on the request, an invalidate request is sent to the other processor requesting the other processor to release ownership of the data. Concurrent to the invalidate request being sent to the other processor, the data is speculatively provided to the requesting processor.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: October 6, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Deanna P. Berger, Christian Jacobi, Robert J. Sonnelitter, III, Craig R. Walters
  • POST COMPLETION EXECUTION IN AN OUT-OF-ORDER PROCESSOR DESIGN
    Publication number: 20200285482
    Abstract: A computer data processing system includes an instruction pipeline having a front end and a back end, a decoding and dispatch unit to dispatch a current instruction; and a pipeline by-pass unit to invoke an out-of-order pipeline by-pass operation. The pipeline by-pass unit by-passes a section of the instruction pipeline such that the current instruction architecturally completes before initiating instruction execution. The computer data processing system further includes a post-completion execution unit that executes the current instruction after the current instruction architecturally completes.
    Type: Application
    Filed: March 8, 2019
    Publication date: September 10, 2020
    Inventors: Avery Francois, Christian Jacobi, Gregory William Alexander
  • PERFORM CRYPTOGRAPHIC COMPUTATION SCALAR MULTIPLY INSTRUCTION
    Publication number: 20200264843
    Abstract: A single architected instruction to perform scalar multiplication for cryptographic operations is obtained. The instruction is executed, and the executing includes determining a scalar multiply function of a plurality of scalar multiply functions supported by the instruction to be performed. Input for the scalar multiply function is obtained, and the input includes at least one source component and a scalar value. The scalar multiply function is performed using the input to provide an output to be used in a cryptographic operation.
    Type: Application
    Filed: February 15, 2019
    Publication date: August 20, 2020
    Inventors: Eric M. Schwarz, Jonathan D. Bradbury, Edward T. Malley, Christian Jacobi
  • COMPUTE DIGITAL SIGNATURE AUTHENTICATION VERIFY INSTRUCTION
    Publication number: 20200267000
    Abstract: A single architected instruction to verify a signed message is executed. The executing includes determining a verify function of a plurality of verify functions supported by the instruction to be performed and obtaining input for the instruction. The input includes a message and a key. Based on the verify function to be performed and the input, a signature of the message is verified.
    Type: Application
    Filed: February 15, 2019
    Publication date: August 20, 2020
    Inventors: Eric M. Schwarz, Jonathan D. Bradbury, Edward T. Malley, Christian Jacobi
  • ADJUSTING THREAD BALANCING IN RESPONSE TO DISRUPTIVE COMPLEX INSTRUCTION
    Publication number: 20200264920
    Abstract: A computer-implemented method is provided and includes allocating, by a processor, an instruction to a first thread, decoding, by the processor, the instruction, determining, by the processor, a type of the instruction based on information obtained by decoding the instruction, and based on determining that the instruction is a disruptive complex instruction, changing a mode of allocating hardware resources to an instruction-based allocation mode. In the instruction-based allocation mode, the processor adjusts allocation of the hardware resources among a first thread and a second thread based on types of instructions allocated to the first and second threads.
    Type: Application
    Filed: February 19, 2019
    Publication date: August 20, 2020
    Inventors: Avery Francois, Gregory William Alexander, Christian Jacobi
  • COMPUTE DIGITAL SIGNATURE AUTHENTICATION SIGN INSTRUCTION
    Publication number: 20200267001
    Abstract: A single architected instruction to produce a signature for a message is obtained. The instruction is executed, and the executing includes determining a sign function of a plurality of sign functions supported by the instruction to be performed. Input for the instruction is obtained, and the input includes a message and a cryptographic key. A signature is produced based on the sign function to be performed and the input. The signature is to be used to verify the message.
    Type: Application
    Filed: February 15, 2019
    Publication date: August 20, 2020
    Inventors: Eric M. Schwarz, Jonathan D. Bradbury, Edward T. Malley, Christian Jacobi
  • COMPUTE DIGITAL SIGNATURE AUTHENTICATION SIGN WITH ENCRYPTED KEY INSTRUCTION
    Publication number: 20200266999
    Abstract: A single architected instruction to produce a signature for a message is executed. The executing includes determining an encrypted sign function of a plurality of encrypted sign functions supported by the instruction to be performed and obtaining input for the instruction. The input includes a message and an encrypted cryptographic key. Based on the encrypted sign function to be performed and the input, a signature to be used to verify the message is produced.
    Type: Application
    Filed: February 15, 2019
    Publication date: August 20, 2020
    Inventors: Eric M. Schwarz, Jonathan D. Bradbury, Edward T. Malley, Christian Jacobi
  • Method and arrangement for saving cache power
    Patent number: 10740240
    Abstract: A computer implemented method for saving cache access power is suggested. The cache is provided with a set predictor logic for providing a generated set selection for selecting a set in the cache, and with a set predictor cache for pre-caching generated set indices of the cache. The method comprises further: receiving a part of a requested memory address; checking, in the set predictor cache, whether the requested memory address is already generated; in the case, that the requested memory address has already been generated: securing that the set predictor cache is switched off; issuing the pre-cached generated set index towards the cache; and securing that only that part of the cache is switched on that is associated with the pre-cached generated set index.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: August 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Christian Jacobi, Markus Kaltenbach, Ulrich Mayer, Johannes C. Reichart, Anthony Saporito, Siegmund Schlechter
  • Methods and systems for predicting virtual address
    Patent number: 10740248
    Abstract: A method or system of translating a virtualized address to a real address is disclosed that includes receiving a virtualized address for translation; generating a predicted intermediate address translation using a portion of the bit field of the virtualized address; determining a predicted real address using the predicted intermediate address or portion thereof; performing a translation of the virtualized address to an actual intermediate address; determining whether the predicted intermediate address is the same as the actual intermediate address; and in response to the predicted intermediate address being the same as the actual intermediate address, providing the predicted real address as the real address.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: August 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: David Campbell, Dwain A. Hicks, Christian Jacobi
  • HANDLING AN INPUT/OUTPUT STORE INSTRUCTION
    Publication number: 20200249943
    Abstract: An input/output store instruction is handled. A data processing system includes a system nest communicatively coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is communicatively coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to an external device which is communicatively coupled to the input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed.
    Type: Application
    Filed: January 29, 2020
    Publication date: August 6, 2020
    Inventors: Christoph Raisch, Marco Kraemer, Frank Siegfried Lehnert, Matthias Klein, Jonathan D. Bradbury, Christian Jacobi, Brenton Belmar, Peter Dana Driever