Abstract: The described implementations relate a Passive Optical Network (PON). In one implementation, the PON includes an Optical Network Unit (ONU) that has at least one transmitter subsystem component and an associated optical transmitter. The at least one transmitter subsystem component may be configured to be in an enabled state during a timeslot period assigned to the ONU for transmitting an upstream data burst and a disabled state after the timeslot ends.

Abstract: A control device for controlling a supply voltage which can be switched between a constant line current operation and a constant line voltage operation, wherein a line current, which consists of a direct current for supplying the terminal and of an alternating current for transmitting information, flows via a subscriber line of a terminal, comprising a sensing circuit for sensing an analogue input voltage dependent on the line current, a subtractor which, in the constant line current operation, subtracts an analogue feedback voltage dependent on an adjustable nominal direct-current value from the sensed input voltage for generating an analogue difference voltage, an analogue/digital converter for converting the generated analogue difference voltage into a digital difference voltage value, a digital low-pass filter for filtering a sequence of control error values out of the generated sequence of difference voltage values, a controller for generating a control value in dependence on the filtered-out sequence of

Abstract: A DC-to-DC converter includes a switching control circuit adapted to provide a control signal having a duty cycle. A switching regulator is adapted to receive both a supply voltage having the first voltage level and the control signal. The switching regulator is further adapted to provide an output signal at the second voltage level as a function of both the supply voltage and the control signal. In addition, a current sensing circuit is adapted to provide at least one alarm signal based the duty cycle of the time-varying signal. Other systems and methods are also disclosed.

Abstract: A control device for controlling a supply voltage which can be switched between a constant line current operation and a constant line voltage operation, wherein a line current, which consists of a direct current for supplying the terminal and of an alternating current for transmitting information, flows via a subscriber line of a terminal, comprising a sensing circuit for sensing an analogue input voltage dependent on the line current, a subtractor which, in the constant line current operation, subtracts an analogue feedback voltage dependent on an adjustable nominal direct-current value from the sensed input voltage for generating an analogue difference voltage, an analogue/digital converter for converting the generated analogue difference voltage into a digital difference voltage value, a digital low-pass filter for filtering a sequence of control error values out of the generated sequence of difference voltage values, a controller for generating a control value in dependence on the filtered-out sequence of

Abstract: The invention provides a transmission apparatus (100) for transmission of electrical signals between a line driver (205), which is connected to a transmission line (201), and a switching center (301), having an analog feedback device (101) for coarse setting of a line voltage level (210) on the transmission line (201), and a digital feedback device (102), which is coupled to the analog feedback device (101) and has a feedback filter device (118), designed such that a filter input signal (404) can be converted to a filter output signal (405) at a rate which is lower than the sampling rate (fa) of an analog/digital converter (104).

Abstract: Audio processing systems and corresponding methods are disclosed, wherein the audio processing system comprises at least one of an analog portion and a digital portion.

Abstract: A CODEC circuit for POTS system comprises a digital circuit for outputting a digital control signal having a first bit width, the digital control signal being indicative of a voltage to be applied to a POTS subscriber line pair. Further, the CODEC circuit comprises a noise shaper coupled to an output of the digital circuit for generating a noise-shaped control signal and a digital-to-analog converter coupled to an output of the noise shaper, the input of the digital-to-analog converter having a second bit width being larger than 1 and smaller than the first bit width.

Abstract: In the case of a device for transmission of telephone signals via a data telecommunications network (2) the analogue signals of a telephone terminal are converted to digital signals for transmission via the data telecommunications network (2) and/or, vice versa, digital signals from the data telecommunications network (2) are converted to analogue signals for transmission via the telephone terminal. In order to monitor the operation of the device, advantageously digital signals arising within the device are analyzed. According to the invention a digital signal is acquired within the device and the characteristics of this, which characterize the amplitude and/or the frequency response of the acquired digital signal, are determined. The determined characteristics are sent out via the data telecommunications network (2). In this way the function of such conversion devices can also be monitored over a greater distance via the data telecommunications network (2) and signals arising therein can be analyzed.

Abstract: Transmission apparatus with variable impedance matching The invention provides a transmission apparatus (100) for transmission of electrical signals between a line driver (205), which is connected to a transmission line (201), and a switching center (301), having an analog feedback device (101) for coarse setting of a line voltage level (210) on the transmission line (201), and a digital feedback device (102), which is coupled to the analog feedback device (101) and has a feedback filter device (118), designed such that a filter input signal (404) can be converted to a filter output signal (405) at a rate which is lower than the sampling rate (fa) of an analog/digital converter (104).

Abstract: In a processor system, different memory means (8), which can in each case comprise a memory stack (9) for the instruction counter, a register (10) for temporarily storing data and status register (11), are provided for various tasks. When an interrupt event (EV) occurs which causes a change from a current task to a new task, a controller (21) switches from the memory means (8) allocated to the old task to the memory means (8) allocated to the new task.

Abstract: A method for resynchronizing a clock signal, includes the steps of defining a presettable clock signal, dividing a first clock signal having a first frequency with a programmable digital frequency divider to produce a second clock signal having a second frequency, measuring the second clock signal with a digital control circuit, and programming a programmable digital frequency divider with the digital control circuit, such that the second clock signal corresponds to the presettable clock signal.

Abstract: A method of using a capacitively coupled interface to increase the integrity of digital signals being transmitted across the interface includes transmitting signals between a first electronic circuit and a second electronic circuit using a capacitively coupled interface, and protecting the integrity of the signals by using a protocol. The protocol preferably includes: Transmitting a signal from the first electronic circuit to the second electronic circuit on the capacitively coupled interface. After the second electronic circuit receives the signal from the first electronic circuit, transmitting a unique synchronization sequence from the second electronic circuit to the first electronic circuit on the capacitively coupled interface. Constructing a status signal that contains information concerning a status of the first electronic circuit.

Abstract: A processor (PR) is connected to the output of a phase comparator (PK) in a phase-locked loop. The processor (PR) calculates the phase shift of an input signal (f.sub.E) within an observation time span (for example, .DELTA.t=0-T) from the phase difference (.DELTA..phi.) at the output of the phase comparator (PK) and the parameters of the phase-locked loop (FT1, PK, FI, VCO, FT2).