Abstract: A mobile antenna that repeatably can be attached and detached by rotation from motor vehicles. The antenna having a receiving portion electrically connected to a base body having a contact area for connecting to motor vehicles. The joined base body and receiving portion being encased in a jacket. The base body having grooves with flank surfaces also encased in the jacket; the grooves aligned in the lengthwise direction of the antenna so that the groove flank surfaces are essentially perpendicular to forces produced when the jacket is rotated for attachment and detachment of the antenna to or from the motor vehicle.

Abstract: A mobile antenna that repeatably can be attached and detached by rotation from motor vehicles. The antenna having a receiving portion electrically connected to a base body having a contact area for connecting to motor vehicles. The joined base body and receiving portion being encased in a jacket. The base body having grooves with flank surfaces also encased in the jacket; the grooves aligned in the lengthwise direction of the antenna so that the groove flank surfaces are essentially perpendicular to forces produced when the jacket is rotated for attachment and detachment of the antenna to or from the motor vehicle.

Abstract: Apparatus and method for producing a jacketed antenna, especially a mobile telephone antenna for motor vehicles, where the jacket is formed about antenna conductive parts in a mold. The mold having a centering pin for insertion in an antenna base body having a mating hole, and an antenna receiving portion attached to the base body so as to be aligned and centered in the mold by the centering pin to assure that the antenna conductive parts are completely encased in the jacketing material.

Abstract: A practical approach for synthesis for million gate ASICs is based on the use of synthesis shells. The synthesis shell is generated by beginning with a gate level description of a fully characterized and optimized block. This gate level description is reduced by removing internal gates to produce a synthesis shell of the synthesized block. The synthesis shell preserves input load and fanout for the block, output delay relative to clock for the block, setup/hold constraints on input signals relative to the clock for the block, and delay from input to output for pass through signals for the block. Such a synthesis shell can be used as a substitute for original design netlists and can be used for hierarchical synthesis in a customer's design environment, or as a deliverable from a provider of ASIC services in order to protect the intellectual property of such a provider.

Abstract: An ASIC design methodology in which portions of the ASIC are implemented in silicon or other suitable semiconductor technology at an early stage in the design flow through the use of a series of interim devices. The invention provides a method in which additional portions or subsystems of the integrated circuit are incorporated into successive versions of the interim device. In this manner, the invention provides for the gradual incorporation of a plurality of architectural subsystems into the integrated device such that the synthesis and verification of each iteration is broken into manageable pieces. In the preferred embodiment, this design method is facilitated by incorporating a programmable portion into the design flow of each interim device such that each interim device includes a custom portion into which the subsystems that have been implemented in silicon are fabricated and a programmable portion.

Abstract: An integrated circuit comprised of a customized circuit portion and a programmable logic portion that is interfaced to the customized circuit. The custom circuit and the programmable circuit are fabricated on a common semiconductor substrate to achieve maximum cost savings and performance advantages over implementations in which an external PLD or other programmable device is interfaced to a custom circuit. Suitably, the customized circuit is designed with an ASIC design flow to optimize the performance, power consumption, and size of the customized circuit. In the presently preferred embodiment, the programmable circuit comprises a plurality of programmable logic cells suitably generated by, in one embodiment, a PLD compiler. Ideally, the relative size and placement of said PLD with respect to said customized circuit are selectable during a design phase of said integrated circuit. This provides flexibility in determining how much of an interim device need be devoted to programmable circuitry.

Abstract: A method for creating a shell to represent a functional block of an IC design comprising of a plurality of interconnected functional blocks. The critical information from a synthesized gate level block is retained in the shell such that when analyzing the static characteristics of another block connected to the block now represented by the shell the analysis is still accurate. At a hierarchial level the present invention provides a method for analyzing the functional blocks of an IC design such that the memory requirement for storing the information of the functional blocks of the IC design is reduced as well as a decrease in run time.

Abstract: Gate level netlists used for timing analysis in integrated circuit design are reduced using a timing shell generator while preserving critical information for timing analysis. After verification of timings, the gate level netlist is convened into a shell containing block boundary information. The function of the shell generator is to delete internal cells meeting a set of criteria. The result is a shell netlist containing a subset of the original netlist. Thus, the design cycle time involved and computing time and resources needed in ASIC development for chips using circuits represented by timing shell netlists are decreased by substituting design verification at the top level of large hierarchical netlists or large flat netlists by bottom up verification procedures using timing shells.