Abstract: In a method of producing a layer arrangement, a substantially carbon-comprising, electrically conductive carbon layer is formed. A protective layer is formed on the carbon layer. An electrically insulating layer is formed on the protective layer, the protective layer protecting the carbon layer from damage during the formation of the electrically insulating layer. Furthermore, a layer arrangement is provided, having a substantially carbon-comprising, electrically conductive carbon layer, a protective layer formed on the carbon layer, and an electrically insulating layer formed on the protective layer, the protective layer being used to avoid damage to the carbon layer by the electrically insulating layer.

Abstract: The present invention relates to a method of fabricating a capacitor in a semiconductor substrate. The capacitor is fabricated such that the capacitor comprises: a trench inside a substrate, the trench having a lower region and an upper region, wherein the trench's diameters in the lower region is larger than in the upper region; a first electrode; a dielectric layer on top of the first electrode; a conductive layer on top of the electric layer, the conductive layer forming a second electrode of the capacitor; and a plug forming a closed cavity inside the lower region.

Abstract: Integrated circuit device comprising a conductive layer and a poly-crystalline silicon layer, wherein the integrated circuit device further comprises an intermediate counter-stress layer. This intermediate counter-stress layer is arranged between the poly-crystalline silicon layer and the conductive layer, and enables stress-reduced crystallization of the poly-crystalline silicon layer. Further, the intermediate counter-stress layer is amorphous at and below a poly-silicon crystallization temperature.

Abstract: A device includes an array of memory cells, which are arranged vertically to a main substrate surface. The array is provided with lower bitlines, wordlines and upper bitlines. The lower and upper bitlines are contact-connected to lower source/drain regions and corresponding upper source/drain regions, respectively, in such a manner that a unique addressing of individual memory cells is possible.

Abstract: A storage capacitor, particularly for use in a storage cell, exhibits two storage electrodes and a dielectric arranged between the two storage electrodes, an intermediate layer essentially consisting of carbon.

Abstract: A storage capacitor includes a first electrode layer, second electrode layer and a dielectric interlayer arranged between the first electrode layer and the second electrode layer. The dielectric interlayer contains a high-k dielectric and at least one silicon-containing component.

Abstract: Integrated circuit device comprising a conductive layer and a poly-crystalline silicon layer, wherein the integrated circuit device further comprises an intermediate counter-stress layer. This intermediate counter-stress layer is arranged between the poly-crystalline silicon layer and the conductive layer, and enables stress-reduced crystallization of the poly-crystalline silicon layer. Further, the intermediate counter-stress layer is amorphous at and below a poly-silicon crystallization temperature.

Abstract: In a method of producing a layer arrangement, a substantially carbon-comprising, electrically conductive carbon layer is formed. A protective layer is formed on the carbon layer. An electrically insulating layer is formed on the protective layer, the protective layer protecting the carbon layer from damage during the formation of the electrically insulating layer. Furthermore, a layer arrangement is provided, having a substantially carbon-comprising, electrically conductive carbon layer, a protective layer formed on the carbon layer, and an electrically insulating layer formed on the protective layer, the protective layer being used to avoid damage to the carbon layer by the electrically insulating layer.

Abstract: In a method for producing a semiconductor structure a substrate is provided, a dielectric layer comprising at least one metal oxide is formed on the substrate, and a nitrided layer is formed from the dielectric layer. The nitrided layer comprises either at least one metal nitride corresponding to the metal oxide or a metal oxynitride. The nitrided layer is removed selectively with respect to the dielectric layer in a predetermined etching medium.

Abstract: The present invention relates to a method of fabricating a capacitor in a semiconductor substrate. The capacitor is fabricated such that the capacitor comprises: a trench inside a substrate, the trench having a lower region and an upper region, wherein the trench's diameters in the lower region is larger than in the upper region; a first electrode; a dielectric layer on top of the first electrode; a conductive layer on top of the electric layer, the conductive layer forming a second electrode of the capacitor; and a plug forming a closed cavity inside the lower region.

Abstract: A memory cell having a trench capacitor, a trench capacitor, and a method is disclosed. In one embodiment, the method for fabricating a trench capacitor with a first capacitor electrode, a first capacitor dielectric, a second capacitor electrode, a second capacitor dielectric and third capacitor electrode, includes connecting the first and third capacitor electrodes. The first and third capacitor electrodes are formed by conformal deposition methods, whereas the first capacitor dielectric, the second capacitor electrode and the second capacitor dielectric are formed by nonconformal deposition methods.