Abstract: A data structure for a jointly utilized memory device, in particular, for inter-process communication, in an application system. The memory device includes a memory cell. The data structure includes a management structure, the management structure being configured to hold a pointer object to the memory cell.

Abstract: A method for providing a piece of data in a communication system. The method includes: allocating a memory means for updating data in the memory means, in particular by a producer, in particular in response to a request signal of the producer; updating the data in the provided memory means with the piece of data; providing the memory means for the purpose of being read out, in particular by a consumer, wherein, in the allocation step, the memory means is allocated as a function of a status of the memory means.

Abstract: A method and system for eliminating implementation timing with respect to a synchronization circuit. A standard library cell having a pair of clock input pins can be connected with at least two asynchronous clock domains of the synchronization circuit in order to measure a timing signal between the flip-flop latches crossing the asynchronous clock domain. A timing delay with respect to each bit pair of the asynchronous clock domain can be determined utilizing a static analysis approach during a layout phase in order to effectively synchronize the asynchronous clock domain. Each bit pair of the asynchronous clock domain can be checked via a static timing analysis tool in order to thereby improve functional accuracy of the synchronization circuit in a wide range of digital logic designs.

Abstract: A method and system for eliminating implementation timing with respect to a synchronization circuit. A standard library cell having a pair of dock input pins can be connected with at least two asynchronous dock domains of the synchronization circuit in order to measure a timing signal between the flip-flop latches crossing the asynchronous clock domain. A timing delay with respect to each bit pair of the asynchronous dock domain can be determined utilizing a static analysis approach during a layout phase in order to effectively synchronize the asynchronous dock domain. Each bit pair of the asynchronous dock domain can be checked via a static timing analysis tool in order to thereby improve functional accuracy of the synchronization circuit in a wide range of digital logic designs.

Abstract: The present invention may relate generally to a circuit for converting a first digital signal having a first sample rate to second digital signal having a second sample rate. The circuit may comprise a cascaded integration-comb filter and a fractional sample rate converter. The fractional sample rate converter may be configured to perform fractional sample rate conversion. A first of the cascaded integrator-comb filter and the fractional sample rate converter may be configured to receive the first signal having the first sample rate and to generate a third digital signal having a third sample rate different from the first and second sample rates. A second of the cascaded integrator-comb filter and the fractional sample rate converter may be configured to receive the third signal having the third sample rate and to generate the second signal having the second sample rate.