Abstract: A 3-D memory module comprising a plurality of packaged integrated memory circuits or devices is mounted to a substrate with integrated pins that are edge-connected on two surfaces where the top surface provides an edge connection from the integrated memory circuits to an orthogonally-mounted memory controller circuit through a wide-word interface. Each integrated memory device can be accessed independently wherein the memory controller is configured to reduce the wide-word interface to a serial interface which is brought to the opposite surface of the memory module for electrical coupling to an external system or printed circuit assembly.

Abstract: Aspects of the present invention provide electronics for controlling and synchronizing operation of electro-active lenses regardless of frame type, size or style. The controlling electronics can be contained within one or more electronic modules positioned within the frame temples and can be removable and reprogrammable and can include inductive charge regions. Conductive links between electronic modules and/or between left and right Sides of the electro-active spectacles can include left and right upper and lower rim portions of the frame, the bridge, conductive layers of the electro-active lenses, the upper and lower grooves of the electro-active lenses, and/or wires embedded within any portion of the frame. Aspects of the present invention also provide chargers for recharging electro-active spectacles of any size, shape or style using adjustable inductive charging cradles to inductively charge electro-active spectacles of the present invention.

Abstract: A memory device such as a solid state memory device have a dual-hardware, secure erase feature. A memory controller operating in a memory controller domain provides general memory management and interface operons. Upon receipt of a trigger signal which may be received from a secure supervisor circuit, a separate processor element that is configured to directly access the raw memory cells in the device bypasses the memory controller domain and executes a separately provided secure erase operating system whereby the raw cell data may be erased and rewritten with a predetermined data pattern and whereby the erase operation at the raw cell level may be verified and reported to the user by the processor.

Abstract: A method is provided to verify that a memory device has been erased and that the device is the originally intended item. Physically uncloneable features of the memory are revealed after erase and form the data for a fingerprint that verifies that the memory has not been exchanged for another memory. A PUF inherent in multiple memory devices included in the memory is revealed upon erase and the PUF is used to create and ID. This ID is compared to the ID for the original unit.

Abstract: A memory device such as a solid state memory device have a dual-hardware, secure erase feature. A memory controller operating in a memory controller domain provides general memory management and interface operons. Upon receipt of a trigger signal which may be received from a secure supervisor circuit, a separate processor element that is configured to directly access the raw memory cells in the device bypasses the memory controller domain and executes a separately provided secure erase operating system whereby the raw cell data may be erased and rewritten with a predetermined data pattern and whereby the erase operation at the raw cell level may be verified and reported to the user by the processor.

Abstract: Aspects of the present invention provide electronics for controlling and synchronizing operation of electro-active lenses regardless of frame type, size or style. The controlling electronics can be contained within one or more electronic modules positioned within the frame temples and can be removable and reprogrammable and can include inductive charge regions. Conductive links between electronic modules and/or between left and right Sides of the electro active spectacles can include left and right upper and lower rim portions of the frame, the bridge, conductive layers of the electro-active lenses, the upper and lower grooves of the electro-active lenses, and/or wires embedded within any portion of the frame. Aspects of the present invention also provide chargers for recharging electro-active spectacles of any size, shape or style using adjustable inductive charging cradles to inductively charge electro-active spectacles of the present invention.

Abstract: A physically uncloneable function (PUF) sense and response module fabricated from a stack of integrated circuit chip layers. At least one of the PUF chips in the stack has a unique identifier resulting from random effects of fabrication processes. The PUF chip generates the fingerprint at power-on resulting that in turn is used to generate a private key. The private key generates a public key used to communicate with the outside world. The encrypted data from the outside world is decrypted with the private key. The public key is stored for comparison with pubic keys generated at subsequent power-up operations. If the key changes, tampering is indicated and a predetermined tamper response event is generated such as the erasing of the contents of a memory.

Abstract: A high capacity, secure and tamper-resistant computer data memory device. The device uses a plurality of dedicated memory controller elements in communication with an anti-tamper module that generates a tamper response when a predetermined tamper event occurs. The tamper response may be provided as the erasure or zeroization of the contents of a memory in the devices such as erasing one or more encryption keys. The elements of the device are preferably provided in a stacked configuration with rerouted I/O pads to obfuscate the I/O and function of the devices in the stack. In one embodiment, a data transfer governance means is provided. In a further embodiment, a current negotiation means is disclosed to permit the device to request a predetermined current from a host device. In a yet further embodiment, a portable safe house computing device is provided.

Abstract: A 3-D LADAR imaging system incorporating stacked microelectronic layers is provided. A reference insert circuit inserts data into the FIFO registers at a preselected location to provide a reference point at which all FIFO shift register data may be aligned to accommodate for timing differences between layers and channels. The bin data representing the photon reflections from the various target surfaces are read out of the FIFO and processed using appropriate circuitry such as a field programmable gate array to create a synchronized 3-D point cloud for creating a 3-D target image.

Abstract: The disclosed invention comprises a substrate having one or more conductive metal traces comprising one or more electrical access leads terminating on a lateral surface of the substrate. A layer or stack of layers comprising one or more integrated circuit chips having one or more access leads in electrical connection with one or more integrated circuit bond pads on the one or more integrated circuit chips is bonded to the substrate. The surface area of the layers is less than the surface area of the substrate so as to define one or more component surface areas on the substrate. The access leads of the layers are oriented to be substantially coplanar and in vertical registration with the access leads of the substrate access leads.

Abstract: Aspects of the present invention provide electronics for controlling and synchronizing operation of electro-active lenses regardless of frame type, size or style. The controlling electronics can be contained within one or more electronic modules positioned within the frame temples and can be removable and reprogrammable and can include inductive charge regions. Conductive links between electronic modules and/or between left and right sides of the electro-active spectacles can include left and right upper and lower rim portions of the frame, the bridge, conductive layers of the electro-active lenses, the upper and lower grooves of the electro-active lenses, and/or wires embedded within any portion of the frame. Aspects of the present invention also provide chargers for recharging electro-active spectacles of any size, shape or style using adjustable inductive charging cradles to inductively charge electro-active spectacles of the present invention.

Abstract: A 3-D LADAR imaging system incorporating stacked microelectronic layers is provided. A light source such as a laser is imaged upon a target through beam shaping optics. Photons reflected from the target are collected and imaged upon a detector array through collection optics. The detector array signals are fed into a multilayer processing module wherein each layer includes detector signal processing circuitry. The detector array signals are amplified, compared to a user-defined threshold, digitized and fed into a high speed FIFO shift register range bin. Dependant on the value of the digit contained in the bins in the register, and the digit's bin location, the time of a photon reflection from a target surface can be determined. A T0 trigger signal defines the reflection time represented at each bin location by resetting appropriate circuitry to begin processing.

Abstract: A 3-D LADAR imaging system incorporating stacked microelectronic layers is provided. A light source such as a laser is imaged upon a target through beam shaping optics. Photons reflected from the target are collected and imaged upon a detector array though collection optics. The detector array signals are fed into a multilayer processing module wherein each layer includes detector signal processing circuitry. The detector array signals are amplified, compared to a user-defined threshold, digitized and fed into a high speed FIFO shift register range bin. Dependant on the value of the digit contained in the bins in the register, and the digit's bin location, the time of a photon reflection from a target surface can be determined. A T0 trigger signal defines the reflection time represented at each bin location by resetting appropriate circuitry to begin processing.

Abstract: A 3-D LADAR imaging system incorporating stacked microelectronic layers is provided. A light source is imaged upon a target through beam shaping optics. Photons reflected from the target are collected and imaged upon a detector array though collection optics. The detector array signals are fed into a multilayer processing module wherein each layer includes detector signal processing circuitry. The detector array signals are amplified, compared to a user-defined threshold, digitized and fed into a high speed FIFO range bin. Dependant on the value of the digit contained in the bins in the register, and the digit's bin location, the time of a photon reflection from a target surface can be determined. A To trigger signal defines the reflection time represented by each bin location by resetting appropriate circuitry to begin processing.

Abstract: A 3-D LADAR imaging system incorporating stacked microelectronic layers is provided. A light source is imaged upon a target through beam shaping optics. Photons reflected from the target are collected and imaged upon a detector array though collection optics. The detector array signals are fed into a multilayer processing module wherein each layer includes detector signal processing circuitry. The detector array signals are amplified, compared to a user-defined threshold, digitized and fed into a high speed FIFO range bin. Dependant on the value of the digit contained in the bins in the register, and the digit's bin location, the time of a photon reflection from a target surface can be determined. A T0 trigger signal defines the reflection time represented by each bin location by resetting appropriate circuitry to begin processing.

Abstract: A 3-D LADAR imaging system incorporating stacked microelectronic layers is provided. A light source is imaged upon a target through beam shaping optics. Photons reflected from the target are collected and imaged upon a detector array though collection optics. The detector array signals are fed into a multilayer processing module wherein each layer includes detector signal processing circuitry. The detector array signals are amplified, compared to a user-defined threshold, digitized and fed into a high speed FIFO range bin. Dependant on the value of the digit contained in the bins in the register, and the digit's bin location, the time of a photon reflection from a target surface can be determined. A T0 trigger signal defines the reflection time represented by each bin location by resetting appropriate circuitry to begin processing.

Abstract: A 3-D LADAR imaging system incorporating stacked microelectronic layers is provided. A light source such as a laser is imaged upon a target through beam shaping optics. Photons reflected from the target are collected and imaged upon a detector array though collection optics. The detector array signals are fed into a multilayer processing module wherein each layer includes detector signal processing circuitry. The detector array signals are amplified, compared to a user-defined threshold, digitized and fed into a high speed FIFO shift register range bin. Dependant on the value of the digit contained in the bins in the register, and the digit's bin location, the time of a photon reflection from a target surface can be determined. A T0 trigger signal defines the reflection time represented at each bin location by resetting appropriate circuitry to begin processing.