Abstract: Apparatus and methods are disclosed, including using a memory controller to monitor at least one parameter related to power level of a host processor of a host device, and dynamically adjusting at least one of a clock frequency and a voltage level of an error-correcting code (ECC) subsystem of the memory controller based on the at least one parameter to control power usage of the host device.

Abstract: Various examples are directed to devices and methods involving a host device and a memory system, the memory system comprising a memory controller and a plurality of memory locations. The memory system may send to the host device a first message describing background operations to be performed at the memory system. The memory system may receive from the host device a second message indicating permission to execute the background operations and may begin to execute at least one background operation.

Abstract: Data can be stored in a computing device as encrypted to prevent the data from being read and/or modified without being decrypted using cryptographic information. To prevent the data from being decrypted in locations other than a secure location, the cryptographic information can be removed logically and physically from the computing device when it is determined that the computing device has left the secure location.

Abstract: Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.

Abstract: Methods, systems, and devices for suspend operation with data transfer to a host system are described. A host system may transmit a read command to a memory system operating in a first mode of operation (e.g., a standard mode associated with a nominal power consumption) indicating for the memory system to transition to a second mode of operation (e.g., a suspend mode associated with a decreased power consumption). Here, the memory system may transmit an image of the memory system stored in volatile memory to the host system and transition the memory system to the second mode. Additionally, the host system may transmit, to the memory system operating in the second mode, a write command including the image and indicating for the memory system to transition to the first mode. Here, the memory system may write the image to the volatile memory and transition to the first mode.

Abstract: Methods, systems, and devices related to techniques for saturating a host interface are described. A set of data stored at a first memory device may be communicated over an interface during a read operation performed in response to receiving a read request associated with the set of data. A control component may determine if the interface entered an idle state during portions of the read operation. Based on detecting an idle state of the interface, the control component may transfer the set of data from the first memory device to a second memory device. After receiving a second read request for the set of data, the memory device may access the set of data from the second memory device and communicate the set of data over the interface, where the interface may remain in a saturated state throughout the second read operation.

Abstract: Devices and techniques are disclosed herein for allowing host-based maintenance of a flash memory device. In certain examples, memory write information can be encrypted at the memory device and provided to the host for updating and maintaining memory device maintenance statistics.

Abstract: Methods, systems, and devices for dynamic power modes for boot-up procedures are described. A memory system may initiate a boot-up procedure according to a predefined first power mode that is associated with a first power consumption. The memory system may then determine whether to perform the boot-up procedure according to the first power mode or a second power mode associated with a different second power consumption. In cases that the memory system receives an indication of the second power mode from the host system, the memory system may perform the boot-up procedure according to the second power mode. Additionally, in cases that the memory system does not receive an indication of the second power mode from the host system, the memory system may perform the boot-up procedure according to the first power mode.

Abstract: Methods, systems, and devices for techniques for controlling command order are described. An entity of a host system, such as a file system, may insert a sequential identifier into commands generated by the entity to indicate an order of the commands. In some examples, the host system may specify a set of commands in a first sequence to be transmitted to the memory system. The host system may subsequently reorder the set of commands in to a second sequence and transmit the set of commands to the memory system. In some cases, following a power-on condition, the memory system may determine a latest valid command of the set of commands. The memory system may subsequently invalidate one or more logical addresses associated with commands having sequence identifiers after the sequence identifier of the latest valid command.

Abstract: Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.

Abstract: Apparatus and methods are disclosed, including using a memory controller to monitor at least one parameter related to power level of a host processor of a host device, and dynamically adjusting at least one of a clock frequency and a voltage level of an error-correcting code (ECC) subsystem of the memory controller based on the at least one parameter to control power usage of the host device.

Abstract: Methods, systems, and devices for exclusion regions for host-side memory address translation are described. In some examples, a host system may be configured to identify regions of logical addresses to be excluded from operating according to logical-to-physical (L2P) address mapping by the host system (e.g., for access commands), including such techniques that may be associated a host performance boosting (HPB) functionality. The host system may signal an indication for a memory system to inhibit communication of L2P mapping table information to the host system for the identified regions, which may inhibit, suppress, or exclude HPB functionality for those identified regions. In some examples, the memory system may continue to support HPB functionality by communicating L2P mapping table information for other regions, such as regions of logical addresses that may be read relatively frequently or may otherwise benefit from address translation at the host system.

Abstract: Methods, systems, and devices for identification and storage of boot information at a memory system are described to support transferring boot information to higher reliability memory storage. A memory system may identify boot information stored at a memory array based on a command received from a host system, which may identify the boot information for the memory system, or based on performing a boot procedure with the host system, in which the boot information may be requested from the memory system. After identifying the boot information stored at the memory array, the memory system may move or transfer the boot information from physical addresses associated with lower reliable memory storage to physical addresses associated with higher reliable memory storage.

Abstract: Methods, systems, and devices for optimized command sequences are described. An apparatus includes a memory array and a controller coupled with the memory array. The controller may be configured to receive a first command indicating a start of a sequence of access commands to store at the controller, then receive a first set of access commands associated with the sequence of access commands, and then receive a second command indicating the end of the sequence of access commands. The controller may also receive a second set of access commands after the command. The controller may execute an operation associated with a third set of access commands of the sequence after receiving the second set of access commands and before receiving the third set of access commands based at least in part on identifying the second set of access commands as starting the sequence of access commands.

Abstract: Methods, systems, and devices supporting switchable lane directions between a host system and a memory system are described. A host system may communicate with a memory system using a set of lanes, where each lane may send information (e.g., commands, operations, data) in a specific direction. In some cases, the host system and memory system may support one or more switchable lanes, where both systems include transmit and receive modules for the lane. According to a bandwidth condition associated with a specific direction satisfying a threshold for reconfiguring a lane, the host system and the memory system may switch a direction configured for a lane. Switching the lane direction may increase the supported bandwidth in a specific direction, for example, from the host system to the memory system (e.g., in a “write optimized” configuration) or from the memory system to the host system (e.g., in a “read optimized” configuration).

Abstract: Methods, systems, and devices for techniques for atomic write operations are described. A memory system may determine a set of pages for an atomic write operation in which data associated with a write command is linked together for writing to a non-volatile memory. The memory system may write, to the non-volatile memory, metadata that indicates the set of pages is associated with the atomic write operation. Based on the metadata, the memory system may determine whether each page of the set of pages has been written with data for the atomic write operation. The memory system may then communicate to a host system an indication of a completion status for the atomic write operation based on determining whether each page of the set of pages has been written with the data for the atomic write operation.

Abstract: Methods, systems, and devices for suspend operation with data transfer to a host system are described. A host system may transmit a read command to a memory system operating in a first mode of operation (e.g., a standard mode associated with a nominal power consumption) indicating for the memory system to transition to a second mode of operation (e.g., a suspend mode associated with a decreased power consumption). Here, the memory system may transmit an image of the memory system stored in volatile memory to the host system and transition the memory system to the second mode. Additionally, the host system may transmit, to the memory system operating in the second mode, a write command including the image and indicating for the memory system to transition to the first mode. Here, the memory system may write the image to the volatile memory and transition to the first mode.

Abstract: Methods, systems, and devices for memory operations are described. A host system may obtain data for writing to a memory system. The host system may send, to the memory system, an indication that the data is to be written to the memory system, and the memory system may remove invalid data at the memory system until the memory system has sufficient resources to store the data. Based on the memory system having sufficient resources, the memory system may delay background operations at the memory system until the data has been written to the memory system. The memory system may also create a restore point based on the memory system having sufficient resources and receiving the data. In other examples, the removal of invalid data at the memory system may be delayed until after the data is written to the memory system.

Abstract: Methods, systems, and devices supporting switchable lane directions between a host system and a memory system are described. A host system may communicate with a memory system using a set of lanes, where each lane may send information (e.g., commands, operations, data) in a specific direction. In some cases, the host system and memory system may support one or more switchable lanes, where both systems include transmit and receive modules for the lane. According to a bandwidth condition associated with a specific direction satisfying a threshold for reconfiguring a lane, the host system and the memory system may switch a direction configured for a lane. Switching the lane direction may increase the supported bandwidth in a specific direction, for example, from the host system to the memory system (e.g., in a “write optimized” configuration) or from the memory system to the host system (e.g., in a “read optimized” configuration).

Abstract: Methods, systems, and devices for copy command for a memory system are described. A method may include storing, within a memory system, data associated with one or more first addresses within an address space. The method may further include receiving a copy command for the data from a host for the memory system. The memory system may associate, in response to the copy command, the data with one or more second addresses within the address space.