Abstract: The present invention relates to a data processing apparatus which comprises a microprogrammable processor 1, a random access control store 4 and a read only control store 5 for storage of microinstructions. The random access control store includes a flag microinstruction (REPmark1) for indicating that another microinstruction (add W, 2, W1), stored in the read only control store 5, is faulty. The control stores are coupled to a multiplexer 8 and are adapted to output the microinstructions in parallel to the multiplexer 8 which is in turn coupled to the processor and which selectively provides output from either the random access control store or the read only control store to the processor 1. The apparatus also includes a decoder coupled to the random access control store for observing the microinstructions output therefrom. The decoder is further coupled to inhibiting logic in the processor and outputs a signal if the flag microinstruction is output from the random access control store.