Abstract: A detection arrangement includes a counter unit which receives a first clock signal and a reference clock signal. The counter unit derives a first data word as a function of a time deviation between clock edges of the first clock signal and the reference clock signal. The detection arrangement further includes a signal processing unit to determine a phase deviation word as a function of the first data word and a second data word, the second data word based on the duration of a clock period of the reference clock signal.

Abstract: A control circuit may be provided. In this case, an output of the control circuit is connected to a control input of a signal generator. Depending on internal signals which identify an operating state of a signal processing device, the control circuit generates a regulating signal at the output. The operating point of the signal generator is thereby set in such a way that a current consumption of the signal processing device is reduced, so that the signal quality is ensured in a sufficient manner.

Abstract: A signal processing device implemented in a semiconductor body includes a frequency conversion device and a converter connected to the frequency conversion device. The conversion device is coupled by a terminal to a terminal on the surface of the semiconductor body. One terminal of the converter is connected to a terminal node of the signal processing device. A signal generator, which is connected by its signal output to a local oscillator input of the frequency conversion device, has a control input for setting its operating point. Furthermore, a control circuit is provided. In this case, an output of the control circuit is connected to the control input of the signal generator. Depending on internal signals which identify an operating state of the signal processing device, the control circuit generates a regulating signal at the output.

Abstract: The invention provides an interface apparatus for data recovery which supplies an analog signal (applied to the input and containing data in line with a coding) having a first component and a second component to a signal processor. From this, the signal processor produces a continuous, demodulated data stream. The data stream is supplied to a connected delay unit, whose output is designed to provide the stored data symbols and whose delay in provision can be set by a signal at a control input. The interface allows a digital modulator to be connected to an analog I/Q interface on a baseband unit.

Abstract: A detection arrangement includes a counter unit which receives a first clock signal and a reference clock signal. The counter unit derives a first data word as a function of a time deviation between clock edges of the first clock signal and the reference clock signal. The detection arrangement further includes a signal processing unit to determine a phase deviation word as a function of the first data word and a second data word, the second data word based on the duration of a clock period of the reference clock signal.

Abstract: A phase locked loop is disclosed and includes a frequency divider circuit with a settable division ratio in a feedback path. The division ratio is produced using a control circuit which, besides an input for supplying the integer and fractional components for the frequency division ratio which is to be set, includes an input for supplying a phase correction signal. To produce the phase correction signal, the phase locked loop further includes a phase correction apparatus. The phase correction signal preferably contains a signal component with an exponential profile, and is supplied to the control circuit for producing a frequency division ratio for the frequency divider circuit such that it compensates for a phase drift in the output signal from the voltage controlled oscillator in the phase locked loop.

Abstract: The phase-locked loop has a pulse generator has a phase detector which is intended to compare a reference signal with an oscillator signal, and a detector output for tapping off a phase comparison signal. The pulse generator is used to produce a pulse-width-modulated pulse signal and has a generator output, from which the pulse-width-modulated pulse signal is tapped off. A selection unit is furthermore provided and is connected, on the input side, to the detector output and to the generator output, and is designed in such a manner that either the phase comparison signal or the pulse signal can be tapped off from an output of the selection unit using a control signal applied to a control input of the selection unit.

Abstract: A phase regulating arrangement or circuit is disclosed, in which, in addition to a frequency divider, which is arranged in the feedback path of the PLL and, provision is made of a further frequency counter. The frequency counter is configured to be readable and is likewise connected to the oscillator output. The frequency counter drives a control unit that selects a desired frequency band of a multiband oscillator. The phase regulating arrangement or circuit described enables very fast settling in conjunction with low phase noise and good integration possibilities.

Abstract: A signal processing device implemented in a semiconductor body includes a frequency conversion device and a converter connected to the frequency conversion device. The conversion device is coupled by a terminal to a terminal on the surface of the semiconductor body. One terminal of the converter is connected to a terminal node of the signal processing device. A signal generator, which is connected by its signal output to a local oscillator input of the frequency conversion device, has a control input for setting its operating point. Furthermore, a control circuit is provided. In this case, an output of the control circuit is connected to the control input of the signal generator. Depending on internal signals which identify an operating state of the signal processing device, the control circuit generates a regulating signal at the output.

Abstract: A phase locked loop is disclosed and includes a frequency divider circuit with a settable division ratio in a feedback path. The division ratio is produced using a control circuit which, besides an input for supplying the integer and fractional components for the frequency division ratio which is to be set, includes an input for supplying a phase correction signal. To produce the phase correction signal, the phase locked loop further includes a phase correction apparatus. The phase correction signal preferably contains a signal component with an exponential profile, and is supplied to the control circuit for producing a frequency division ratio for the frequency divider circuit such that it compensates for a phase drift in the output signal from the voltage controlled oscillator in the phase locked loop.

Abstract: A phase regulating arrangement or circuit is disclosed, in which, in addition to a frequency divider, which is arranged in the feedback path of the PLL and, provision is made of a further frequency counter. The frequency counter is configured to be readable and is likewise connected to the oscillator output. The frequency counter drives a control unit that selects a desired frequency band of a multiband oscillator. The phase regulating arrangement or circuit described enables very fast settling in conjunction with low phase noise and good integration possibilities.

Abstract: The phase-locked loop has a pulse generator has a phase detector which is intended to compare a reference signal with an oscillator signal, and a detector output for tapping off a phase comparison signal. The pulse generator is used to produce a pulse-width-modulated pulse signal and has a generator output, from which the pulse-width-modulated pulse signal is tapped off. A selection unit is furthermore provided and is connected, on the input side, to the detector output and to the generator output, and is designed in such a manner that either the phase comparison signal or the pulse signal can be tapped off from an output of the selection unit using a control signal applied to a control input of the selection unit.

Abstract: The invention provides an interface apparatus for data recovery which supplies an analog signal (applied to the input and containing data in line with a coding) having a first component and a second component to a signal processor. From this, the signal processor produces a continuous, demodulated data stream. The data stream is supplied to a connected delay unit, whose output is designed to provide the stored data symbols and whose delay in provision can be set by a signal at a control input. The interface allows a digital modulator to be connected to an analog I/Q interface on a baseband unit.