Abstract: A poller including an output (S), as well as a first (E1), a second (E2), and a third (E3) input, receiving respectively a first (E.sub.s 1), a second (E.sub.s 2), and a third (E.sub.s 3) signal, which are identical during normal operation. The poller further includes a two-channel diverter (AIG1) provided with an active input (A), a quiescent input (R), a control input (EC) and a common output (SC). The quiescent input (R) and the active input (A) of the diverter (AIG1) are respectively connected to the first (E1) and second (E2) inputs of the poller, whereas the common output (S) of the diverter (AIG1) is connected to the output (S) of the poller. A first monitor (M1) with two inputs (X, Y), branched between the second and third inputs (E2, E3) of the poller, is used to measure the deviation between the second (E.sub.s 2) and third (E.sub.s 3) signals and to control the diverter (AIG1).

Abstract: A three-input signal selector formulates two output signals from three input signals. The selector is useful in pollers of various types.

Abstract: Device for synchronizing two constant high frequency digital pulse sequences S and R.sub.f comprising a first oscillator producing the frequency sequence R.sub.f at the fundamental frequency f and a second oscillator producing the frequency sequence of pulses S also at the frequency f. The second oscillator is a ring oscillator having three loops of inverted logic gates connected in series and corresponding respectively to the frequency f (used if synchronism exists), to a higher frequency f.sub.1 (used if there is a phase lag) and a lower frequency f.sub.2 (used if there is a phase lead) with the choice of the operating loop being made by a multiplexer on the basis of instructions from a phase detector permanently comparing the synchronism, lead or lag state of the sequence S compared with the sequence R.sub.f.