Abstract: Methods for measuring the sensitivity of a data packet signal receiver are provided by varying the power level or modulation or both of a received data packet signal in a predetermined controlled sequence of data packet signals.

Abstract: An extended power ramp table for a power amplifier control loop in a time division multiple access (TDMA) communication system includes a power profile data table and a control data table. The power profile data are used to control transitions of the power amplifier circuit between its on and off states to minimize the number and power levels of spurious and other undesired signals generated by such on and off circuit state transitions. The control data are used to programmably control various performance characteristics of the control loop for the power amplifier circuit, such as controlling the gain of the driver amplifier for the power amplifier control (or reference) signal, controlling the gain and offset of the feedback amplifier for the control loop, and selectively providing a bias current for an external power detection diode. By making the control data user programmable, maximum flexibility in controlling the power amplifier control loop can be achieved.

Abstract: A frequency synthesizer with a digital frequency lock loop (FLL) having a fast frequency lock time uses a frequency counter circuit in the feedback loop to count the output signal frequency and produce frequency count data. A modulation control circuit provides modulation data and a corresponding modulation control signal for modulating the FLL signal source. A microprocessor processes the frequency count data along with the modulation data to provide a frequency control signal for controlling the nominal, or center, frequency of the FLL signal source. By processing these data together, thereby accounting for the amount of modulation applied to the FLL signal source, the center frequency can be maintained more consistently notwithstanding the presence of modulation within the feedback loop signal.

Abstract: In a SOI structure according to the invention, a substrate region directly adjacent and underlying the buried oxide layer is doped with a dopant having a conductivity type opposite that of the substrate. This produces a junction between the doped layer and the substrate. Appropriately biasing this junction creates a depletion layer, which effectively extends the width of the buried oxide layer deep into the substrate, thereby reducing parasitic capacitance in the SOI structure, particularly for inductors, interconnects, and other passive circuit elements. Reducing parasitic capacitance reduces associated substrate losses and RC propagation delays. These benefits become increasingly important at high frequencies encountered in RF wireless communication and high speed digital applications.

Abstract: A voltage sample and hold circuit for use as part of a low leakage charge pump circuit in a phase lock loop (PLL). During an inactive state of the charge pumping function, a MOSFET switch that normally connects the charge pump output to the loop filter preceding the voltage controlled oscillator (VCO) of the PLL is opened, e.g., for open loop modulation of the VCO. Meanwhile, the sample and hold circuit which has sampled the voltage at the input side of the MOSFET switch now maintains that voltage, thereby forcing a zero-voltage difference across the MOSFET switch. This zero-voltage difference virtually eliminates subthreshold leakage current through the MOSFET switch, thereby significantly reducing loss of charge in the loop filter due to such leakage current. This ensures a significantly more constant DC bias at the input to the VCO and, therefore, a more stable output center, or carrier, frequency from the PLL during open loop modulation.

Abstract: A control circuit for causing a phase lock loop (PLL) frequency synthesizer to achieve a fast phase lock time while also providing improved loop performance during normal phase locked operation. The phase locking time of the PLL is minimized by initially configuring the PLL to operate in a fractional mode with high frequency signals presented to the inputs of the loop phase detector, thereby producing a fast phase lock time. Once the PLL has achieved phase lock, its operation mode is transitioned to either an integer mode or an open loop mode without loss of phase lock, thus causing lower frequency signals or no signals, respectively, to be presented to the inputs of the loop phase detector and thereby significantly reducing spurious signal tones.

Abstract: In a SOI structure according to the invention, a substrate region directly adjacent and underlying the buried oxide layer is doped with a dopant having a conductivity type opposite that of the substrate. This produces a junction between the doped layer and the substrate. Appropriately biasing this junction creates a depletion layer, which effectively extends the width of the buried oxide layer deep into the substrate, thereby reducing parasitic capacitance in the SOI structure, particularly for inductors, interconnects, and other passive circuit elements. Reducing parasitic capacitance reduces associated substrate losses and RC propagation delays. These benefits become increasingly important at high frequencies encountered in RF wireless communication and high speed digital applications.

Abstract: A circuit and a method are provided for reducing power consumption in a phase-locked loop (PLL) by controlling how long the bias current for the charge pump is turned on. In such a circuit, a bias check circuit that indicates when the bias current has stabilized, and a self-adjusting control circuit including an internal counter are provided to measure how long the bias current takes to start up when the PLL is locked. Then the self-adjusting control circuit prevents the bias current from turning on until there is just enough time for it to stabilize before a charge pump event. A default control circuit is also provided to turn the bias current on for specified intervals when the PLL is out of lock.

Abstract: A current mirror model is provided for designing a continuous-time filter with reduced filter noise. The current mirror model includes an input branch having a voltage V.sub.in across a series circuit including a voltage source and a resistor of resistance value R.sub.m. The voltage source has a voltage value substantially equal to the value 4kTR.sub.m, where k is the Boltzmann constant and T is the temperature. An output branch is coupled to the input branch. The output branch has a first current source and a second current source. The first current source is controlled by the voltage V.sub.in and sources a current substantially equal to a transconductance G.sub.m of the output branch times the voltage V.sub.in. The output branch transconductance G.sub.m has a transconductance value substantially less than a value of an input branch conductance 1/R.sub.m. The second current source, coupled in parallel to the first current source, sources a current substantially equal to the value 4kTG.sub.m.