Abstract: A system operable to perform scaleable arbitration and prioritization of multiple interrupts. The present invention presents a solution that is theoretically indefinitely scaleable to accommodate any number of interrupt sources. The invention provides for orthogonal scalability of interrupt sources—a feature absolutely non-existent in the prior art. The propagation time of an interrupt within the system is predictable and nearly independent of the number of priority levels or the number of interrupt sources. In addition, the invention presents a novel solution to support multiple interrupt sources having a common priority level. The solution is scaleable in two dimensions, namely, modularity in the number of interrupt sources that can be supported and scaleable in the number of priority levels that can be supported. The solution significantly reduces the deleterious effects of hardware latency in slowing interrupt processing.

Abstract: A system operable to perform scaleable arbitration and prioritization of multiple interrupts. The present invention presents a solution that is theoretically indefinitely scaleable to accommodate any number of interrupt sources. The invention provides for orthogonal scalability of interrupt sources—a feature absolutely non-existent in the prior art. The propagation time of an interrupt within the system is predictable and nearly independent of the number of priority levels or the number of interrupt sources. In addition, the invention presents a novel solution to support multiple interrupt sources having a common priority level. The solution is scaleable in two dimensions, namely, modularity in the number of interrupt sources that can be supported and scaleable in the number of priority levels that can be supported. The solution significantly reduces the deleterious effects of hardware latency in slowing interrupt processing.