Abstract: An apparatus for the cardio-synchronized stimulation of skeletal or smooth muscle, but excluding the heart muscles, in a counterpulsation mode of a patient.

Abstract: An apparatus for the cardio-synchronised stimulation of skeletal or smooth muscle, but excluding the heart muscles, in a counterpulsation mode of a patient.

Abstract: An apparatus for the cardio-synchronized stimulation of skeletal or smooth muscle, but excluding the heart muscles, in a counterpulsation mode of a patient.

Abstract: An apparatus for the cardio-synchronised stimulation of skeletal or smooth muscle, but excluding the heart muscles, in a counterpulsation mode of a patient.

Abstract: An apparatus for the cardio-synchronized stimulation of skeletal or smooth muscle, but excluding the heart muscles, in a counterpulsation mode of a patient.

Abstract: An apparatus for the cardio-synchronised stimulation of skeletal or smooth muscle, but excluding the heart muscles, in a counterpulsation mode of a patient.

Abstract: An apparatus for the cardio-synchronized stimulation of skeletal or smooth muscle, but excluding the heart muscles, in a counterpulsation mode of a patient.

Abstract: An apparatus for the cardio-synchronised stimulation of skeletal or smooth muscle, but excluding the heart muscles, in a counterpulsation mode of a patient having a heart and a cardiovascular system.

Abstract: A system for generating addresses for a digital signal processor in which the program instructions include a code for accessing a memory associated with said processor. An address calculation circuit calculates each access address to the memory on the basis of operation codes designated by the address generation code of one of the instructions and of the content of one address register selected from said address registers. Each address generation code defines an operation code to be sent to the calculation circuit. Each of the address registers is further associated with a configuration register designated at the same time as the address register by the address generation code, and each of the configuration registers contains a set of predefined operation codes, each adapted to command a predetermined calculation operation in the calculation circuit.

Abstract: A neural network having layers of neurons divided into sublayers of neurons. The values of target neurons in one layer are calculated from sublayers of source neurons in a second underlying layer. It is therefore always possible to use for this calculation the same group of weights to be multiplied by respective source neurons related thereto and situated in the underlying layer of the neural network.

Abstract: A timekeeper equipped with a radio reception device capable of decoding Radio Data System (RDS) information and including a time base, a display for displaying time data supplied by the time base, and an adjustment control for correcting the time data. The radio reception device includes a frequency locking loop for delivering RDS type data derived from a RDS spectrum received on a high-frequency carrier; and a controller which, on the basis of the delivered RDS type data, controls the adjustment control to ensure time setting of the timekeeper. The timekeeper is portable and the radio reception device rejects the spectrum received from a frequency modulated transmitter supplying RDS data, except for the frequency band containing RDS type data.

Abstract: The invention concerns a timepiece, in particular a wristwatch comprising a middle (1), a watch movement (4) housed in the middle, a transmission and/or reception circuit (5) associated with said movement and an antenna (9) connected to said transmission and/or reception circuit. The invention is characterized in that the antenna (9) consists in an electrically conductive solid single-piece mass (10) shaped at least partly like a ring, said mass being arranged at the periphery of said middle (1). Furthermore, the antenna is connected to the transmission and/or reception circuit via a conductor (18) passing through the wall of the middle (1) over part of its thickness.

Abstract: The invention concerns a timekeeper equipped with a radio reception device capable of decoding a Radio Data System (RDS) information (7) and comprising a time base (1), means (5) for displaying time data supplied by said time base, and means (2) for correcting said time data. The radio reception device (7) comprises means (10) for delivering RDS type data derived from a RDS spectrum received on a high-frequency carrier; and control means (4, 6, 19) which, on the basis of the delivered RDS type data control the correcting means (2) to ensure time setting of the timekeeper. The invention is characterised in that the timekeeper is designed to be portable and the radio reception device (7) further includes means (10) for rejecting the spectrum received from a frequency modulated transmitter supplying RDS data, except for the frequency band in which are contained RDS type data.

Abstract: The program instructions include a code for generating addresses for accessing one memory associated with said processor. An address calculation circuit calculates each access address to said memory on the basis of operation codes designated each time by the address generation code of the instructions and of the content of one address register selected from said address registers, and its associated offset and/or a modulo registers. Each address generation code of each instruction define an operation codes to be sent to said calculation circuit. Each of said address registers is further associated with a configuration register designated at the same time as said address register by said address, generation code, each of said configuration registers contains a set of predefined operation codes, each adapted to command a predetermined calculation operation in said calculation circuit and to be transferred to said calculation means, according to said address generation code.

Abstract: The values of target neurons are calculated for sublayers of target neurons It is therefore always possible to use for this calculation the same group of weights to be multiplied by respective source neurons related thereto and situated in the underlying layer of the neural network.

Abstract: An adiabatic logic circuit includes bidirectional transfer members to which input variables of the circuit are applied and which are connected between a first circuit terminal connected to a clock generator whose clock signal also powers the circuit and a second circuit terminal forming its output and which assumes two logic levels as a function of the input variables. The circuit has a third terminal connected to the second terminal via its inherent capacitance and precharges the second terminal to a potential corresponding to one of the logic levels outside active phases of the clock signal.

Abstract: A random access memory comprises a matrix made up of cells arranged in rows and columns and the cells are addressed row by row. Each cell of a row is connected to first and second bit lines and at least the first bit line is subdivided into a plurality of sections connected to respective inputs of an output logic gate. The memory includes read/write control circuits which apply the following logic functions to each of the first and second bit lines directly or indirectly and selectively, according to whether a required operation is a write or a read. Sel.((W.D) or {overscore (W)})) is applied to the first bit line, whilst Sel.W.D is applied to both the first and second bits lines, where “Sel” is a cell selection signal representative of the address, “W” is a write command, {overscore (W)} is a read command, “D” is the data to be written into the addressed cell and “.” indicates the AND function.

Abstract: A D-type master-slave flip-flop includes a master unit receiving an input variable and producing two first intermediate variables, a transfer unit including at least two logic gates and a clock connection connected to one input of each of the gates, which are adapted to supply two second intermediate variables as a function of the input variable and the clock signal and are looped to the master unit, and a slave unit to form at least one output variable. Another input of a first gate of the transfer unit is connected to the master unit to receive directly the true value of one of the variables supplied by the master unit. Another input of the second gate of the transfer unit is connected to the master unit to receive therefrom the complement of the same variable. The second intermediate variables are independent of each other. The flip-flop has the advantage that it is insensitive to the slopes of the flanks of the clock signals.

Abstract: The disclosure relates to microprocessors and, more particularly, to a system for organizing and a method for the sequencing of the circuits of a microprocessor. The instruction registers are connected in chains and an inhibiting device is associated with each instruction register. Each inhibiting device has its inputs connected to the inputs of the associated register and to the clock circuit a provides and signal for the loading of the associated instruction register when it detects a predetermined combination of digits in the associated register.

Abstract: In this device, each processor (P1 to P3) is associated with at least one dressable space (R1 to R3), whereas all the processors and all the addressable spaces are in communication by way of a common communication bus (BC).Between all the processors and each addressable space is connected an intercommunicating connection node (N1 to N3), each connection node including control means (LC, D1, D2) forensuring priority of access of any processor to its own addressable space; andensuring a hierarchy of priority of access to the addressable spaces of the other processors among said plurality of processors.