Patents by Inventor Christian R. Bonhôte
Christian R. Bonhôte has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10270030Abstract: The present disclosure generally relates to a structure, system, and method for manufacturing an electrical component for a memory device. For example, depositing alternating layers of conductive and insulator materials over an etch stop layer to create a vertical stack, etching a trench through the vertical stack to expose the etch stop layer, electroplating the conductive layers using a plating material based on a desired electrical behavior, and forming a connection between the plating materials for each of the conductive layers.Type: GrantFiled: October 5, 2016Date of Patent: April 23, 2019Assignee: Western Digital Technologies, Inc.Inventors: Christian R. Bonhôte, Jeffrey Lille
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Publication number: 20170025476Abstract: The present disclosure generally relates to a structure, system, and method for manufacturing an electrical component for a memory device. For example, depositing alternating layers of conductive and insulator materials over an etch stop layer to create a vertical stack, etching a trench through the vertical stack to expose the etch stop layer, electroplating the conductive layers using a plating material based on a desired electrical behavior, and forming a connection between the plating materials for each of the conductive layers.Type: ApplicationFiled: October 5, 2016Publication date: January 26, 2017Inventors: Christian R. Bonhôte, Jeffrey LILLE
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Publication number: 20170005263Abstract: The present disclosure generally relates to a structure, system, and method for manufacturing an electrical component for a memory device. For example, depositing alternating layers of conductive and insulator materials over an etch stop layer to create a vertical stack, etching a trench through the vertical stack to expose the etch stop layer, electroplating the conductive layers using a plating material based on a desired electrical behavior, and forming a connection between the plating materials for each of the conductive layers.Type: ApplicationFiled: June 30, 2015Publication date: January 5, 2017Inventors: Christian R. BONHÔTE, Jeffrey LILLE
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Publication number: 20150105006Abstract: Embodiments of the present invention generally relate to a blade for isolating devices within a wafer and the method of isolating. The blade has a core material, a cutting material disposed on the core material, and a plating material covering a portion of the core and cutting materials. The edge of the blade is not covered by the plating material. During operation, a portion of the plating material is removed to expose the underlying core and cutting materials based on the wearing of the core and cutting materials at the edge of the blade.Type: ApplicationFiled: October 11, 2013Publication date: April 16, 2015Applicant: HGST NETHERLANDS B.V.Inventors: Jacey R. BEAUCAGE, Christian R. BONHÔTE, Trevor W. OLSON
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Patent number: 8673161Abstract: Methods for fabricating a device component are provided. A substrate comprising a RIE stop layer, an oxide layer formed on the RIE stop layer, and a RIE-able layer formed on the oxide layer may be provided. A resist layer may be patterned on the RIE-able layer. A metal layer may be formed on portions of the RIE-able layer that are not covered by the resist layer. The resist layer may be removed and an RIE performed to remove exposed portions of the RIE-able layer and portions of the oxide layer beneath the exposed portions of the RIE-able layer. Thereafter, the metal layer may be removed, and the component may be formed in an opening in the oxide layer formed during the RIE.Type: GrantFiled: December 29, 2008Date of Patent: March 18, 2014Assignee: HGST Netherlands B.V.Inventors: Christian R. Bonhôte, Jeffrey S. Lille, Ricardo Ruiz
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Patent number: 8449752Abstract: Methods for fabrication of magnetic write heads, and more specifically to fabrication of magnetic poles and trailing magnetic pole steps. A write pole may first be patterned on a substrate. Then a side gap material may be patterned along sidewall portions of the write pole. Thereafter, a masking layer may be deposited and patterned to expose a portion of the write pole. A trailing magnetic pole step may be formed on the exposed portion of the write pole.Type: GrantFiled: September 30, 2009Date of Patent: May 28, 2013Assignee: HGST Netherlands B.V.Inventors: Christian R. Bonhôte, Trevor W. Olson, Aron Pentek, Thomas J. A. Roucoux
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Patent number: 8432637Abstract: A magnetic head according to one embodiment includes a side gap layer comprising primarily silicon nitride, wherein outer sides of the side gap layer taper away from one another from a leading end of the side gap layer towards a trailing end of the side gap layer; a seed layer above the silicon nitride side gap layer; and a magnetic pole on the seed layer. A method for forming a magnetic head according to one embodiment includes etching a channel in a silicon oxide layer; forming a side gap layer comprising primarily silicon nitride in the channel; forming a seed layer above the side gap layer; plating a pole on the seed layer; and removing the silicon oxide layer by wet etching. Additional systems and methods are also presented.Type: GrantFiled: November 10, 2010Date of Patent: April 30, 2013Assignee: HGST Netherlands B.V.Inventors: Christian R. Bonhote, Kanaiyalal C. Patel
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Publication number: 20120113544Abstract: A magnetic head according to one embodiment includes a side gap layer comprising primarily silicon nitride, wherein outer sides of the side gap layer taper away from one another from a leading end of the side gap layer towards a trailing end of the side gap layer; a seed layer above the silicon nitride side gap layer; and a magnetic pole on the seed layer. A method for forming a magnetic head according to one embodiment includes etching a channel in a silicon oxide layer; forming a side gap layer comprising primarily silicon nitride in the channel; forming a seed layer above the side gap layer; plating a pole on the seed layer; and removing the silicon oxide layer by wet etching. Additional systems and methods are also presented.Type: ApplicationFiled: November 10, 2010Publication date: May 10, 2012Applicant: Hitachi Global Storage Technologies Netherlands B.V.Inventors: Christian R. Bonhote, Kanaiyalal C. Patel
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Publication number: 20110076393Abstract: Methods for fabrication of magnetic write heads, and more specifically to fabrication of magnetic poles and trailing magnetic pole steps. A write pole may first be patterned on a substrate. Then a side gap material may be patterned along sidewall portions of the write pole. Thereafter, a masking layer may be deposited and patterned to expose a portion of the write pole. A trailing magnetic pole step may be formed on the exposed portion of the write pole.Type: ApplicationFiled: September 30, 2009Publication date: March 31, 2011Inventors: Christian R. Bonhôte, Trevor W. Olson, Aron Pentek, Thomas J. A. Roucoux
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Publication number: 20100252440Abstract: Methods and structures for the electroplating on ultra-thin seed layers are disclosed. A dual layer structure is utilized, consisting of a thicker, highly conductive layer surrounding device structures. Within the device die, an ultra-thin seed layer is employed, which is electrically coupled to the conduction layer. Using this technique, electroplating of critical device structures can be carefully controlled and made uniform across the full diameter of the wafer. The technique also allow for the deployment of ultra-thin seed layers of varying thickness and composition in different locations within the circuit device, or in different die on the wafer.Type: ApplicationFiled: June 9, 2010Publication date: October 7, 2010Inventors: Christian R. Bonhote, Jeffrey S. Lille, Xhavin Sinha
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Patent number: 7770285Abstract: A magnetic read/write head is produced with an insert layer between the substrate and the magnetic transducer. The insert layer has a lower coefficient of thermal expansion than the substrate, which reduces the temperature pole tip recession (T-PTR) of the head because the insert layer is an intervening layer between the substrate and magnetic transducer. The insert layer is produced by plating, e.g., an Invar layer over the substrate prior to fabricating the magnetic transducer. The Invar layer is annealed and the structure planarized prior to depositing a non-magnetic gap layer followed by the fabrication of the magnetic transducer.Type: GrantFiled: March 28, 2008Date of Patent: August 10, 2010Assignee: Hitachi Global Storage Technologies Netherlands B.V.Inventors: Christian R. Bonhote, Malika D. Carter, David A. Dudek, Wen-Chien D. Hsiao, John W. Lam, Vladimir Nikitin
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Publication number: 20100163520Abstract: Methods for fabricating a device component are provided. A substrate comprising a RIE stop layer, an oxide layer formed on the RIE stop layer, and a RIE-able layer formed on the oxide layer may be provided. A resist layer may be patterned on the RIE-able layer. A metal layer may be formed on portions of the RIE-able layer that are not covered by the resist layer. The resist layer may be removed and an RIE performed to remove exposed portions of the RIE-able layer and portions of the oxide layer beneath the exposed portions of the RIE-able layer. Thereafter, the metal layer may be removed, and the component may be formed in an opening in the oxide layer formed during the RIE.Type: ApplicationFiled: December 29, 2008Publication date: July 1, 2010Inventors: Christian R. Bonhote, Jeffrey S. Lille, Ricardo Ruiz
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Publication number: 20090195920Abstract: A method of reducing flux leakage between a main pole and a wrap around shield (WAS) is provided. A gap underneath a main pole is etched. Magnetic material is deposited in the gap. A layer of nonmagnetic material is deposited on the magnetic material, wherein the layer of nonmagnetic material reduces flux leakage between the main pole and the WAS.Type: ApplicationFiled: January 31, 2008Publication date: August 6, 2009Inventors: Christian R. Bonhote, Jeffrey S. Lille, Vladimir Nikitin, Aron Pentek
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Patent number: 7459198Abstract: An electroplated film is deposited over a substrate with a plating frame pattern that includes a plating field defined by a plurality of individual features. By dividing the plating field into a plurality of individual features, the delamination force at any location on the plating field is greatly reduced. Thus, a film with a large stress, such as a high moment film, may be plated to a greater thickness than is possible with conventionally plated films.Type: GrantFiled: May 28, 2004Date of Patent: December 2, 2008Assignee: Hitachi Global Storage Technologies Netherlands B.V.Inventors: Christian R. Bonhote, Heather K. DeSimone, John W. Lam, Matthew W. Last, Edward Hin Pong Lee, Ian R. McFadyen
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Publication number: 20080172862Abstract: A magnetic read/write head is produced with an insert layer between the substrate and the magnetic transducer. The insert layer has a lower coefficient of thermal expansion than the substrate, which reduces the temperature pole tip recession (T-PTR) of the head because the insert layer is an intervening layer between the substrate and magnetic transducer. The insert layer is produced by plating, e.g., an Invar layer over the substrate prior to fabricating the magnetic transducer. The Invar layer is annealed and the structure planarized prior to depositing a non-magnetic gap layer followed by the fabrication of the magnetic transducer.Type: ApplicationFiled: March 28, 2008Publication date: July 24, 2008Inventors: Christian R. Bonhote, Malika D. Carter, David A. Dudek, Wen-Chien D. Hsiao, John W. Lam, Vladimir Nikitin
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Publication number: 20080149490Abstract: Methods and structures for the electroplating on ultra-thin seed layers are disclosed. A dual layer structure is utilized, consisting of a thicker, highly conductive layer surrounding device structures. Within the device die, an ultra-thin seed layer is employed, which is electrically coupled to the conduction layer. Using this technique, electroplating of critical device structures can be carefully controlled and made uniform across the full diameter of the wafer. The technique also allow for the deployment of ultra-thin seed layers of varying thickness and composition in different locations within the circuit device, or in different die on the wafer.Type: ApplicationFiled: December 26, 2006Publication date: June 26, 2008Inventors: Christian R. Bonhote, Jeffrey S. Lille, Xhavin Sinha