Abstract: Virtual disk drive architecture. A novel approach is presented by which a virtual design system allows for the design, development, and testing of memory storage devices including hard disk drives (HDDs). A virtual disk drive architecture allows for the implementation and emulation of a full HDD system. All of the pieces of the HDD system (e.g., including both the read channel and the controller functionalities) are included and implemented to allow a designer to develop and test certain portions within the system. In some embodiments, one or more field programmable gate arrays (FPGAs) are employed to implement a hard drive (HD) controller in an all digital implementation. Various combinations including circuit boards and FPGAs can be employed to emulate an entire HDD system. In even other embodiments, one or more sockets, and appropriate interfacing, are included to allow the testing of actual chips within the virtual disk drive architecture.

Abstract: Disclosed is a method and apparatus for flexibly converting an electrical parallel digital data signal to a serial optical digital data signal for transmission along a fiber optic cable and then subsequent conversion back to a parallel electrical digital data signal. An input conditioner circuit is used to set a ratio between a transmission link clock rate and a sample clock rate such that the ratio determines the number of bits being transmitted for a sample word thus enhancing the flexibility of the device to different sampling rates. Each individual sample word is a frame of data which includes a single frame bit set up in a 4-bit frame pattern. A first frame bit is a sync acquisition bit comprised of an alternating sequence of "0"s and "1"s, a second and fourth parity bit computed from the parity of the previous two words of data, and a third channel identification bit. An output conditioner circuit receives the serial stream of data bits to convert it back to a parallel data format.

Abstract: A switching system comprised of input, intermediate and output switch matrices. There are r n.times.m input matrices, r m.times.n output matrices with m r.times.r intermediate switching matrices. Signals are switched from inputs at the input matrices through the intermediate switch matrices and are output through the output matrices.