Abstract: An analog-to-digital converter (ADC) includes a loop filter having an input for receiving an analog input signal; a quantizer having an input coupled to an output of the loop filter, and an output for providing a digital output signal; and a digital-to-analog converter (DAC) having an input coupled to an output of the quantizer, and an output coupled to the loop filter, wherein the DAC includes at least one always-on DAC element, and a plurality of on-demand DAC elements.

Abstract: An analog-to-digital converter (ADC) includes a loop filter having an input for receiving an analog input signal; a quantizer having an input coupled to an output of the loop filter, and an output for providing a digital output signal; and a digital-to-analog converter (DAC) having an input coupled to an output of the quantizer, and an output coupled to the loop filter, wherein the DAC includes at least one always-on DAC element, and a plurality of on-demand DAC elements.

Abstract: A controlled oscillator Analog-to-Digital Converter (ADC) includes an analog interface configured for receiving an analog differential input signal, and configured for providing a differential control signal; first and second controlled oscillators configured for receiving the differential control signal; and a frequency-to-digital converter having a first input coupled to an output of the first controlled oscillator, a second input coupled to an output of the second controlled oscillator, and an output for providing a digital output signal proportional to the analog differential input signal, wherein the analog interface or at least one of the first and second controlled oscillators is configured for receiving at least one disturb signal to prevent locking between the first and second controlled oscillators.

Abstract: A controlled oscillator Analog-to-Digital Converter (ADC) includes an analog interface configured for receiving an analog differential input signal, and configured for providing a differential control signal; first and second controlled oscillators configured for receiving the differential control signal; and a frequency-to-digital converter having a first input coupled to an output of the first controlled oscillator, a second input coupled to an output of the second controlled oscillator, and an output for providing a digital output signal proportional to the analog differential input signal, wherein the analog interface or at least one of the first and second controlled oscillators is configured for receiving at least one disturb signal to prevent locking between the first and second controlled oscillators.

Abstract: In accordance with an embodiment, a method of operating a switched capacitor circuit includes pre-charging a capacitor using a voltage buffer having an input coupled to an input node of the switched capacitor circuit and an output coupled to the capacitor, coupling the input node to the capacitor, wherein a first charge is collected on the capacitor, and integrating the first charge using an integrator.

Abstract: Representative implementations of devices and techniques provide analog to digital conversion of an analog input. A multistage modulator using a feed-forward technique can alternately convert integrated samples of the analog input to digital representations. For example, the modulator is arranged to alternately output the digital representations to form a digital representation of the analog input.

Abstract: Representative implementations of devices and techniques provide analog to digital conversion of an analog input. A multistage modulator using a feed-forward technique can alternately convert integrated samples of the analog input to digital representations. For example, the modulator is arranged to alternately output the digital representations to form a digital representation of the analog input.

Abstract: In accordance with an embodiment, a method includes activating a first semiconductor switch having a first switch node coupled to a first input of a bootstrap circuit, a second switch node, and a control node coupled to a first end of a capacitor of the bootstrap circuit. A first end of the capacitor is coupled to the first input of the bootstrap circuit and a second end of the capacitor is set to a first voltage. Next, the first end of the capacitor is decoupled from the first input of the bootstrap circuit, and the second end of the capacitor is set to a second voltage. The control node is boosted to a first activation voltage that turns on the first semiconductor switch.

Abstract: In accordance with an embodiment, a circuit includes an analog chopping circuit having a first input coupled to a system input and a second input coupled to a first chopping signal, an oversampled data converter having an input coupled to an output of the analog chopping circuit, where the oversampled data converter is configured to produce an oversampled digital signal at an output of the oversampled data converter. The circuit further includes a digital filter having an input coupled to the output of the oversampled data converter, and a digital chopping circuit including a first input coupled to the output of the oversampled data converter, and a second input coupled to a second chopping signal. The digital filter is configured to filter quantization noise generated by the oversampled data converter.

Abstract: In accordance with an embodiment, a circuit includes an analog chopping circuit having a first input coupled to a system input and a second input coupled to a first chopping signal, an oversampled data converter having an input coupled to an output of the analog chopping circuit, where the oversampled data converter is configured to produce an oversampled digital signal at an output of the oversampled data converter. The circuit further includes a digital filter having an input coupled to the output of the oversampled data converter, and a digital chopping circuit including a first input coupled to the output of the oversampled data converter, and a second input coupled to a second chopping signal. The digital filter is configured to filter quantization noise generated by the oversampled data converter.

Abstract: In an embodiment, a circuit includes a forward path circuit having an auto-zero switch coupled between an input of an amplifier and an output of the amplifier, a first chopping circuit having an input coupled to an input of the forward path circuit and an output coupled to the input of the amplifier, and a second chopping circuit having an input coupled to the output of the amplifier and an output coupled to an output of the forward path circuit. The circuit further includes a feedback circuit that has a feedback switch, a feedback capacitor including a first end coupled to an output of the amplifier, a third chopping circuit coupled between the input of the forward path circuit and a first end of a feedback switch, and a fourth chopping circuit coupled between a second end of the feedback switch and a second end of the feedback capacitor.

Abstract: In accordance with an embodiment, a method includes activating a first semiconductor switch having a first switch node coupled to a first input of a bootstrap circuit, a second switch node, and a control node coupled to a first end of a capacitor of the bootstrap circuit. A first end of the capacitor is coupled to the first input of the bootstrap circuit and a second end of the capacitor is set to a first voltage. Next, the first end of the capacitor is decoupled from the first input of the bootstrap circuit, and the second end of the capacitor is set to a second voltage. The control node is boosted to a first activation voltage that turns on the first semiconductor switch.

Abstract: In an embodiment, a circuit includes a forward path circuit having an auto-zero switch coupled between an input of an amplifier and an output of the amplifier, a first chopping circuit having an input coupled to an input of the forward path circuit and an output coupled to the input of the amplifier, and a second chopping circuit having an input coupled to the output of the amplifier and an output coupled to an output of the forward path circuit. The circuit further includes a feedback circuit that has a feedback switch, a feedback capacitor including a first end coupled to an output of the amplifier, a third chopping circuit coupled between the input of the forward path circuit and a first end of a feedback switch, and a fourth chopping circuit coupled between a second end of the feedback switch and a second end of the feedback capacitor.

Abstract: The present invention provides a Delay Locked Loop circuit having: a delay device for generating at least one delayed clock signal from an input clock signal; a phase detector for comparing the delayed clock signal with the input clock signal; a first control device for generating a first control signal for influencing a delay time of the delay device; a device for generating a signal Q, whose frequency is proportional to the reciprocal of the delay time of the delay device; a device for evaluating the signal Q and generating an output signal; and a second control device for modifying the first control signal in accordance with the output signal. The present invention likewise provides a method for generating a control signal of a Delay Locked Loop circuit.

Abstract: The present invention provides a DLL (Delay-Locked Loop) circuit having: a delay device (1) for generating at least one delayed clock signal (7) from an input clock signal (6); a phase detector (2) for comparing the delayed clock signal (7) with the input clock signal (6); a first control device (3, 4) for generating a first control signal (5) for influencing a delay time of the delay device (1); a device (12) for generating a signal Q (Q), whose frequency is proportional to the reciprocal of the delay time (Delay) of the delay device (1); a device (13, 23) for evaluating the signal Q (Q) and generating an output signal (17); and a second control device (15) for modifying the first control signal in accordance with the output signal (17). The present invention likewise provides a method for generating a control signal of a DLL circuit.