Abstract: A computing system receives a video stream of a game. The computing system generates tracking data corresponding to the video stream using one or more artificial intelligence models. The computing system generates interactive video data by combining the video stream of the game with the tracking data. The computing system causes a media player to render graphics corresponding to the tracking data over the video stream by sending the interactive video data to a client device executing the media player.

Abstract: In a method for the automatic guidance, e.g., parking, of a motor vehicle, which has a driving device for driving the motor vehicle, braking equipment for braking the motor vehicle, as well as a transmission device, in a normal operation, the braking equipment carrying out automatic braking during the automatic guidance, it is provided that, when a fault of the braking equipment occurs during the automatic guidance, an emergency operation is carried out, in which the motor vehicle is braked automatically to a standstill only by using the driving device and/or the transmission device.

Abstract: The invention relates to a one-time programmable memory device. In order to make such a memory device particular simple and reliable, it is proposed that the device comprises a MOS selection transistor T1 and a MOS memory transistor T2 connected in series between a voltage supply line BL and ground Gnd. The device further comprises programming means for applying predetermined voltages Vsel, Vctrl, Vprog to the gate of the selection transistor T1, to the gate of the memory transistor T2 and to the voltage supply line BL. The applied voltages Vsel, Vctrl, Vprog are selected such that they force the memory transistor T2 into a snap-back mode resulting in a current thermally damaging the drain junction of the memory transistor T2. The invention relates equally to a corresponding method for programming a one time programmable memory.

Abstract: A vehicle stabilizing system, for motor vehicles in particular, includes a control unit in which a stabilization control algorithm is stored, a sensor system for detecting present actual values of vehicle state variables, and at least one actuator for implementing a stabilizing intervention when an unstable situation is detected. In order to be able to adapt the vehicle stabilizing system to different types of surfaces, a device is provided which supplies the control unit with information concerning the nature of the surface and at least one controller variable of the stabilization control algorithm is changed as a function of the supplied surface information.

Abstract: A vehicle stabilizing system, for motor vehicles in particular, includes a control unit in which a stabilization control algorithm is stored, a sensor system for detecting present actual values of vehicle state variables, and at least one actuator for implementing a stabilizing intervention when an unstable situation is detected. In order to be able to adapt the vehicle stabilizing system to different types of surfaces, a device is provided which supplies the control unit with information concerning the nature of the surface and at least one controller variable of the stabilization control algorithm is changed as a function of the supplied surface information.

Abstract: The invention relates to an arrangement for improving the ESD protection in an integrated circuit. In order to achieve an effective use of chip area, it is proposed to connect a passive component between the bonding pad and an integrated circuit, said passive component being arranged over an electrically non-conductive layer and under the bonding pad. In the event of damage to the bonding pad when bonding or testing, only the passive component, at most, is short-circuited, but the functionality of the output driver stage and of the integrated circuit remains unaffected.

Abstract: Text Integrated circuit device (20) comprising a silicon substrate (21), integrated devices (22) with contacts (23.1, 23.2), an isolating layer (24) at least partially covering the integrated devices (22) and comprising conducting areas (24.1, 24.2) which establish a conductive path to the contacts (23.1, 23.2) of the integrated devices (22). A metallization level (25) with metal lines (26.1, 26.2, 26.3, 26.4) is provided which connect to one of the contacts (23.2). The metal lines (26.1, 26.2, 26.3, 26.4) are situated above the isolating layer (24). A passivation layer (27)—situated above the metallization level (25)—comprises at least two contact areas (28.1, 28.2) for partially exposing at least two of the metal lines (26.2, 26.4). A bump bridge (29) comprising a conductive, low-resistance material, is situated on the passivation layer (27). The bump bridge (29) has a high aspect ratio and provides for a conductive connection between at least two of the metal lines (26.2, 26.4).

Abstract: The present invention relates to an integrated circuit, comprising:

Abstract: The invention relates to an arrangement for improving the ESD protection in an integrated circuit. In order to achieve an effective use of chip area, it is proposed to connect a passive component between the bonding pad and an integrated circuit, said passive component being arranged over an electrically non-conductive layer and under the bonding pad. In the event of damage to the bonding pad when bonding or testing, only the passive component, at most, is short-circuited, but the functionality of the output driver stage and of the integrated circuit remains unaffected.

Abstract: An arrangement for improving the ESD protection in a CMOS buffer includes a plurality of PMOS transistors (31 to 37) and a plurality of NMOS transistors (41-47) which are connected in series with the PMOS transistors and have a finger width WN which is larger than the finger width WP of the PMOS transistors in order to be capable of withstanding an increased current load in the case of an electrostatic discharge.

Abstract: The invention relates to an arrangement for improving the ESD protection in a CMOS buffer which includes a plurality of PMOS transistors (31 to 37) and a plurality of NMOS transistors (41-47) which are connected in series with the PMOS transistors and have a finger width WN which is larger than the finger width WP of the PMOS transistors in order to be capable of withstanding an increased current load in the case of an electrostatic discharge.