Patents by Inventor Christian Rouet
Christian Rouet has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11351586Abstract: An apparatus and a method for producing an elongated profiled part, in which a profiled strip is produced from a flat strip by rolling and the profiled strip is embossed in sections, by means of which at least one longitudinal section of the profiled strip is offset relative to at least one other longitudinal section in a direction perpendicular to the longitudinal direction of the profiled strip, and with which method the strip is trimmed in such a way that, after the embossing, the longitudinal sections that are offset relative to each other have different cross-sections. In order to increase the reproducibility of the method, before the profiling, the flat strip is trimmed in such a way that by means of the embossing of the trimmed and profiled strip, the longitudinal sections that are offset relative to each other have different cross-sections.Type: GrantFiled: December 21, 2015Date of Patent: June 7, 2022Assignee: voestalpine Krems GmbHInventor: Christian Rouet
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Patent number: 11225038Abstract: A method for manufacturing a semifinished product or component is disclosed in which a metal support embodied as a split strip is covered with at least one prepreg containing a thermally cross-linkable thermosetting matrix with endless fibers, the thermosetting matrix of the prepreg is pre-cross-linked by means of heating, and the metal support covered with the pre-cross-linked prepreg is formed into a semifinished product or component by means of roll forming. In order to enable plastic deformation in fiber-reinforced regions of the metal support, it is proposed that during the pre-cross-linking of the thermosetting matrix of the prepreg, its matrix is transferred into a viscosity state that is higher than its minimum viscosity and prior to reaching its gel point, the prepreg is formed together with the metal support.Type: GrantFiled: December 12, 2016Date of Patent: January 18, 2022Assignees: voestalpine Stahl GmbH, voestalpine Metal Forming GmbHInventors: Carola Eyssell, Rüdiger Heinritz, Reiner Kelsch, Gerhard Mayrhofer, Christian Rouet, Johannes Riegler
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Patent number: 11098385Abstract: The invention relates to a method for continuously roller-forming and hardening sheet steel in which a sheet steel strip is continuously roller-formed into a profile in a roller-profiling unit, characterized in that the roller-formed profile strand is preheated to a temperature below the austenite starting temperature (Ac1) and the roller-formed profile strand is then heated across subregions of its cross-section and/or subregions of its length to a temperature above AC3, with the roller-formed profile strand being acted on with tension at least during the heating of subregions to a temperature >AC3.Type: GrantFiled: October 12, 2016Date of Patent: August 24, 2021Assignee: VOESTALPINE KREMS GMBHInventors: Alfred Seyr, Christian Rouet
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Patent number: 10974469Abstract: A method for manufacturing a semifinished product or part is disclosed in which a metal support embodied as a metal sheet or blank is covered with at least one prepreg containing a thermally cross-linkable thermosetting matrix with endless fibers, the thermosetting matrix of the prepreg is pre-cross-linked by means of heating, and the metal support covered with the pre-cross-linked prepreg is formed into a semifinished product or part by means of deep drawing or stretch deep drawing. In order to enable plastic deformation in fiber-reinforced regions of the metal support, it is proposed that during the pre-cross-linking of the thermosetting matrix of the prepreg, its matrix is transferred into a viscosity state that is higher than its minimum viscosity and prior to reaching its gel point, the prepreg is formed together with the metal support.Type: GrantFiled: December 12, 2016Date of Patent: April 13, 2021Assignee: voestalpine Stahl GmbHInventors: Carola Eyssell, Rüdiger Heinritz, Reiner Kelsch, Gerhard Mayrhofer, Christian Rouet, Johannes Riegler
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Publication number: 20180370162Abstract: A method for mar manufacturing a semifinished product or part is disclosed in which a metal support embodied as a metal sheet or blank is covered with at least one prepreg containing a thermally cross-linkable thermosetting matrix with endless fibers, the thermosetting matrix of the prepreg is pre-cross-linked by means of heating, and the metal support covered with the pre-cross-linked prepreg is formed into a semifinished product or part by means of deep drawing or stretch deep drawing. In order to enable plastic deformation in fiber-reinforced regions of the metal support, it is proposed that during the pre-cross-linking of the thermosetting matrix of the prepreg, its matrix is transferred into a viscosity state that is higher than its minimum viscosity and prior reaching its gel point, the prepreg is formed together with the metal support.Type: ApplicationFiled: December 12, 2016Publication date: December 27, 2018Inventors: Carola Eyssell, Rüdiger Heinritz, Reiner Kelsch, Gerhard Mayrhofer, Christian Rouet, Johannes Riegler
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Publication number: 20180354207Abstract: A method for manufacturing a semifinished product or component is disclosed in which a metal support embodied as a split strip is covered with at least one prepreg containing a thermally cross-linkable thermosetting matrix with endless fibers, the thermosetting matrix of the prepreg is pre-cross-linked by means of heating, and the metal support covered with the pre-cross-linked prepreg is formed into a semifinished product or component by means of roll forming, in order to enable plastic deformation in fiber-reinforced regions of the metal support, it is proposed that during the pre-cross-linking of the thermosetting matrix of the prepreg, its matrix is transferred into a viscosity state that is higher than its minimum viscosity and prior to reaching its gel point, the prepreg is formed together with the metal support.Type: ApplicationFiled: December 12, 2016Publication date: December 13, 2018Inventors: Carola Eyssell, Rüdiger Heinritz, Reiner Kelsch, Gerhard Mayrhofer, Christian Rouet, Johannes Riegler
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Publication number: 20180305782Abstract: The invention relates to a method for continuously roller-forming and hardening sheet steel in which a sheet steel strip is continuously roller-formed into a profile in a roller-profiling unit, characterized in that the roller-formed profile strand is preheated to a temperature below the austenite starting temperature (Ac1) and the roller-formed profile strand is then heated across subregions of its cross-section and/or subregions of its length to a temperature above AC3, with the roller-formed profile strand being acted on with an axial tensile stress at least during the heating of subregions to a temperature >AC3.Type: ApplicationFiled: October 12, 2016Publication date: October 25, 2018Inventors: Alfred SEYR, Christian ROUET
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Patent number: 10008029Abstract: Updating depth related graphics data is described. Geometric primitives are processed. Pixels are generated from the primitives based on the processing, each of which has at least one corresponding depth value. Culling is performed on a first group of the pixels, based on a representation of the at least one depth related value corresponding to each. Pixels may be discarded based on the culling and upon which a second group of pixels remain. A depth related raster operations function is performed, in which data is transacted with a depth buffer. The culling function is updated in relation to the transacting. The updating is performed on the basis of a granularity, which characterizes the culling function.Type: GrantFiled: May 31, 2013Date of Patent: June 26, 2018Assignee: Nvidia CorporationInventors: Christian Amsinck, Eric B. Lum, Barry Rodgers, Tony Louca, Christian Rouet, Jonathan Dunaisky
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Patent number: 9916680Abstract: Techniques are disclosed for suppressing access to a depth processing unit associated with a graphics processing pipeline. The method includes receiving a graphics primitive from a first pipeline stage associated with the graphics processing pipeline. The method further includes determining that the graphics primitive is visible over one or more graphics primitives previously rendered to a frame buffer, and determining that the depth buffer is in a read-only mode. The method further includes suppressing an operation to transmit the graphics primitive to the depth processing unit. One advantage of the disclosed technique is that power consumption is reduced within the GPU by avoiding unnecessary accesses to the depth processing unit.Type: GrantFiled: October 12, 2012Date of Patent: March 13, 2018Assignee: NVIDIA CORPORATIONInventors: Christian Amsinck, Christian Rouet, Tony Louca
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Publication number: 20170348748Abstract: An apparatus and a method for producing an elongated profiled part, in which a profiled strip is produced from a flat strip by rolling and the profiled strip is embossed in sections, by means of which at least one longitudinal section of the profiled strip is offset relative to at least one other longitudinal section in a direction perpendicular to the longitudinal direction of the profiled strip, and with which method the strip is trimmed in such a way that, after the embossing, the longitudinal sections that are offset relative to each other have different cross-sections. In order to increase the reproducibility of the method, before the profiling, the flat strip is trimmed in such a way that by means of the embossing of the trimmed and profiled strip, the longitudinal sections that are offset relative to each other have different cross-sections.Type: ApplicationFiled: December 21, 2015Publication date: December 7, 2017Inventor: Christian Rouet
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Patent number: 9286647Abstract: A computer-implemented method for drawing graphical objects within a graphics processing pipeline is disclosed. The method includes determining that a bypass mode for a first primitive is a no-bypass mode. The method further includes rasterizing the first primitive to generate a first set of rasterization results. The method further includes generating a first set of colors for the first set of rasterization results via a pixel shader unit. The method further includes rasterizing a second primitive to generate a second set of rasterization results. The method further includes generating a second set of colors for the second set of rasterization results without the pixel shader unit performing any processing operations on the second set of rasterization results. The method further includes transmitting the first set of pixel colors and the second set of pixel colors to a raster operations (ROP) unit for further processing.Type: GrantFiled: March 12, 2013Date of Patent: March 15, 2016Assignee: NVIDIA CorporationInventors: Eric B. Lum, Justin Cobb, Rui M. Bastos, Christian Rouet
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Patent number: 9183609Abstract: A technique for efficiently rendering content reduces each complex blend mode to a series of basic blend operations. The series of basic blend operations are executed within a recirculating pipeline until a final blended value is computed. The recirculating pipeline is positioned within a color raster operations unit of a graphics processing unit for efficient access to image buffer data.Type: GrantFiled: December 20, 2012Date of Patent: November 10, 2015Assignee: NVIDIA CorporationInventors: Rui Bastos, Mark J. Kilgard, William Craig McKnight, Jerome F. Duluk, Jr., Pierre Souillot, Dale L. Kirkland, Christian Amsinck, Joseph Detmer, Christian Rouet, Don Bittel
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Publication number: 20140354634Abstract: Updating depth related graphics data is described. Geometric primitives are processed. Pixels are generated from the primitives based on the processing, each of which has at least one corresponding depth value. Culling is performed on a first group of the pixels, based on a representation of the at least one depth related value corresponding to each. Pixels may be discarded based on the culling and upon which a second group of pixels remain. A depth related raster operations function is performed, in which data is transacted with a depth buffer. The culling function is updated in relation to the transacting. The updating is performed on the basis of a granularity, which characterizes the culling function.Type: ApplicationFiled: May 31, 2013Publication date: December 4, 2014Inventors: Christian AMSINCK, Eric B. LUM, Barry RODGERS, Tony LOUCA, Christian ROUET, Jonathan DUNAISKY
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Publication number: 20140267318Abstract: A computer-implemented method for drawing graphical objects within a graphics processing pipeline is disclosed. The method includes determining that a bypass mode for a first primitive is a no-bypass mode. The method further includes rasterizing the first primitive to generate a first set of rasterization results. The method further includes generating a first set of colors for the first set of rasterization results via a pixel shader unit. The method further includes rasterizing a second primitive to generate a second set of rasterization results. The method further includes generating a second set of colors for the second set of rasterization results without the pixel shader unit performing any processing operations on the second set of rasterization results. The method further includes transmitting the first set of pixel colors and the second set of pixel colors to a raster operations (ROP) unit for further processing.Type: ApplicationFiled: March 12, 2013Publication date: September 18, 2014Applicant: NVIDIA CORPORATIONInventors: Eric B. LUM, Justin COBB, Rui M. BASTOS, Christian ROUET
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Publication number: 20140176568Abstract: A technique for efficiently rendering content reduces each complex blend mode to a series of basic blend operations. The series of basic blend operations are executed within a recirculating pipeline until a final blended value is computed. The recirculating pipeline is positioned within a color raster operations unit of a graphics processing unit for efficient access to image buffer data.Type: ApplicationFiled: December 20, 2012Publication date: June 26, 2014Applicant: NVIDIA CORPORATIONInventors: Rui BASTOS, Mark J. Kilgard, William Craig McKnight, Jerome F. Duluk, Pierre Souillot, Dale L. Kirkland, Christian Amsinck, Joseph Detmer, Christian Rouet, Don Bittel
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Publication number: 20140104267Abstract: Techniques are disclosed for suppressing access to a depth processing unit associated with a graphics processing pipeline. The method includes receiving a graphics primitive from a first pipeline stage associated with the graphics processing pipeline. The method further includes determining that the graphics primitive is visible over one or more graphics primitives previously rendered to a frame buffer, and determining that the depth buffer is in a read-only mode. The method further includes suppressing an operation to transmit the graphics primitive to the depth processing unit. One advantage of the disclosed technique is that power consumption is reduced within the GPU by avoiding unnecessary accesses to the depth processing unit.Type: ApplicationFiled: October 12, 2012Publication date: April 17, 2014Applicant: NVIDIA CORPORATIONInventors: Christian AMSINCK, Christian ROUET, Tony LOUCA
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Patent number: 7852341Abstract: A method and system for patching instructions in a 3-D graphics pipeline. Specifically, in one embodiment, instructions to be executed within a scheduling process for a shader pipeline of the 3-D graphics pipeline are patchable. A scheduler includes a decode table, an expansion table, and a resource table that are each patchable. The decode table translates high level instructions to an appropriate microcode sequence. The patchable expansion table expands a high level instruction to a program of microcode if the high level instruction is complex. The resource table assigns the units for executing the microcode. Addresses within each of the tables can be patched to modify existing instructions and create new instructions. That is, contents in each address in the tables that are tagged can be replaced with a patch value of a corresponding register.Type: GrantFiled: October 5, 2004Date of Patent: December 14, 2010Assignee: Nvidia CorporationInventors: Christian Rouet, Rui Bastos, Lordson Yue
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Patent number: 7852340Abstract: A scalable shader architecture is disclosed. In accord with that architecture, a shader includes multiple shader pipelines, each of which can perform processing operations on rasterized pixel data. Shader pipelines can be functionally removed as required, thus preventing a defective shader pipeline from causing a chip rejection. The shader includes a shader distributor that processes rasterized pixel data and then selectively distributes the processed rasterized pixel data to the various shader pipelines, beneficially in a manner that balances workloads. A shader collector formats the outputs of the various shader pipelines into proper order to form shaded pixel data. A shader instruction processor (scheduler) programs the individual shader pipelines to perform their intended tasks.Type: GrantFiled: December 14, 2007Date of Patent: December 14, 2010Assignee: NVIDIA CorporationInventors: Rui M. Bastos, Karim M. Abdalla, Christian Rouet, Michael J.M. Toksvig, Johnny S Rhoades, Roger L. Allen, John Douglas Tynefield, Jr., Emmett M. Kilgariff, Gary M. Tarolli, Brian Cabral, Craig Michael Wittenbrink, Sean J. Treichler
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Patent number: 7646389Abstract: Methods and systems for texture mapping in a computer-implemented graphics pipeline are described. A sample group is identified as including a divergent pixel. A determination is made whether an operand of an instruction executing on the divergent pixel satisfies a condition. A scheme for determining a level of detail for the texture mapping is selected depending on whether or not the condition is satisfied.Type: GrantFiled: May 18, 2005Date of Patent: January 12, 2010Assignee: NVIDIA CorporationInventors: Christian Rouet, Emmett M. Kilgariff, Rui M. Bastos, Wei-Chao Chen
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Patent number: 7624255Abstract: A system and method controls the scheduling of program instructions included in a shader program for execution by a processing pipeline. One or more fence instructions may be inserted into the shader program. Each fence instruction specifies a constraint that is applied to control the scheduling of another program instruction in the shader program. Controlling the scheduling of program instructions for execution by the processing pipeline may result in a more efficient use of computing resources and improved performance.Type: GrantFiled: March 9, 2005Date of Patent: November 24, 2009Assignee: NVIDIA CorporationInventors: Christian Rouet, Rui M. Bastos, Emmett M. Kilgariff