Abstract: A low power, low noise amplifier system includes at least one amplifier having first and second differential input terminals, first and second differential output terminals and providing a differential output; first and second input capacitors interconnected with the first and second differential amplifier input terminals; first and second feedback circuits containing first and second feedback capacitors, respectively, interconnected with the amplifier differential input and output terminals; an input chopper switch circuit for receiving a low frequency differential input and selectively, alternately swapping those low frequency differential inputs through the input capacitors to the differential input terminals of the amplifier; an output chopper switch for receiving and selectively, alternately swapping the amplifier differential outputs synchronously with the input chopper switch circuit; and a low pass filter responsive to the swapped differential outputs for providing a low noise, low power amplification

Abstract: A low power, low noise amplifier system includes at least one amplifier having first and second differential input terminals, first and second differential output terminals and providing a differential output; first and second input capacitors interconnected with the first and second differential amplifier input terminals; first and second feedback circuits containing first and second feedback capacitors, respectively, interconnected with the amplifier differential input and output terminals; an input chopper switch circuit for receiving a low frequency differential input and selectively, alternately swapping those low frequency differential inputs through the input capacitors to the differential input terminals of the amplifier; an output chopper switch for receiving and selectively, alternately swapping the amplifier differential outputs synchronously with the input chopper switch circuit; and a low pass filter responsive to the swapped differential outputs for providing a low noise, low power amplification

Abstract: A switching voltage converter, suitably a boost converter, employs an n-type transistor, preferably an NMOS FET, as a series switch, with its drain coupled to the cathode of the converter's diode and its source coupled to the converter's output node. A charge pump driven by the converter's switching voltage provides a voltage Von at the NMOS FET's gate input sufficient to turn the FET on. A series switch controller is arranged to, in response to a control signal, hold the NMOS FET off such that the converter's output voltage Vout is approximately zero regardless of the status of input voltage Vin, or allow the NMOS device to be turned on by Von.

Abstract: A dual voltage switch enables the generation of a pulse which toggles between user-provided first and second voltages (V1 and V2), for which the positive and/or negative slew rates are programmable by means of a user-provided capacitance. A first switch conducts a current I1 between V1 and a common output node in response to a first control voltage, and a second switch conducts a current I2 between V2 and the common output node in response to a second control voltage. A capacitance C is connected to the common output node. A control circuit alternately provides the first and second control voltages such that the common output node is pulled up to V1 at a transfer rate of I1/C when the first control voltage is provided, and pulled down to V2 at a transfer rate of ?I2/C when the second control voltage is provided.