Abstract: A device and method are disclosed, whereby the normally complicated and difficult frequency determination is achieved by simply arranged and executed measures, namely by means of larger, smaller and/or equal comparisons and a counting of certain events. The invention further relates to arrangements whereby the noise signal level, or the influence thereof on the verification to be carried out is reduced.

Abstract: In the line terminating device, which is provided for transmitting and receiving narrowband low-frequency voice signals and broadband data signals at a higher frequency, the analog reception path is subdivided into two separate analog paths (32, 33) for voice and data using a balance filter (49), which is used for data signal echo cancellation. In the transmission direction, the voice signal path and the data signal path are separated in the digital part by means of digital filters (43, 45). The invention is used for voice and data signal separation in xDSL methods, for example, ADSL.Lite.

Abstract: In the broadband network access device for transmitting narrowband, low-frequency voice signals and broadband, higher-frequency data signals, the voice data is sampled in the data clock pattern and subsequently decimated. The transmission of the data which has already been decimated to the voice clock to the voice DSP (DSP) is still carried out in the data clock pattern. The conversion to the voice clock pattern is carried out in a synchronization interface (SM), directly upstream of the voice DSP. The same applies correspondingly in the opposite direction of transmission. The invention is used in xDSL methods, for example ADSL.Lite.

Abstract: The invention relates to a tuning circuit for tuning a filter stage, which has an RC element (1) with an RC time constant (?), with the RC time constant (?) being the product of the resistance of a resistor (R1) in the RC element (1) and the capacitance of a capacitor (C1), which is connected in series with the resistor (R1), in the RC element (1), having a comparator (10) for comparison of the voltage which is produced at the potential node (4) between the resistor (R1) and the capacitor (C1), with a reference ground voltage; and having a controller (15) which varies the charge on the capacitor (C1) in the RC element (1) until the comparator (10) indicates that the voltage which is produced at the potential node (4) is equal to the reference ground voltage, with the controller (15) switching a capacitor array (26) as a function of the charge variation time, which capacitor array (26) is connected in parallel with the capacitor (C1) in the RC element (1), in order to compensate for any discrepancy between the

Abstract: The invention relates to a multistage differential amplifier having an input stage, at which a differential input voltage is present, a load connected to the input stage, a CMFB circuit and an output stage, at which an amplified differential output voltage is output. In order to improve the stability of a common-mode regulating loop, a current source is provided, which additionally feeds current into the regulating loop and thereby ensures that a control voltage for the load does not fall below a predetermined value.

Abstract: The invention relates to a tuning circuit for tuning a filter stage, which has an RC element (1) with an RC time constant (&tgr;), with the RC time constant (&tgr;) being the product of the resistance of a resistor (R1) in the RC element (1) and the capacitance of a capacitor (C1), which is connected in series with the resistor (R1), in the RC element (1), having a comparator (10) for comparison of the voltage which is produced at the potential node (4) between the resistor (R1) and the capacitor (C1), with a reference ground voltage; and having a controller (15) which varies the charge on the capacitor (C1) in the RC element (1) until the comparator (10) indicates that the voltage which is produced at the potential node (4) is equal to the reference ground voltage, with the controller (15) switching a capacitor array (26) as a function of the charge variation time, which capacitor array (26) is connected in parallel with the capacitor (C1) in the RC element (1), in order to compensate for any discrepancy bet

Abstract: A sigma-delta analog-to-digital converter includes an integrator and a dither signal generator for generating a digital dither signal, and a plurality of comparators for converting an analog signal received from the integrator into an output digital value. A digital logic unit is in data communication with the digital dither signal and the comparators. The digital logic unit is configured to change the output digital value on the basis of the digital dither signal.

Abstract: A device and method are disclosed, whereby the normally complicated and difficult frequency determination is acheived by simply arranged and executed measures, namely by menas of larger, smaller and/or equal comparisons and a counting of certain events. The invention further relates to arrangements whereby the noise signal level, or the influence thereof on the verification to be carried out is reduced.

Abstract: A sigma-delta analog-to-digital converter includes an integrator and a dither signal generator for generating a digital dither signal, and a plurality of comparators for converting an analog signal received from the integrator into an output digital value. A digital logic unit is in data communication with the digital dither signal and the comparators. The digital logic unit is configured to change the output digital value on the basis of the digital dither signal.

Abstract: The invention relates to a multistage differential amplifier having an input stage, at which a differential input voltage is present, a load connected to the input stage, a CMFB circuit and an output stage, at which an amplified differential output voltage is output. In order to improve the stability of a common-mode regulating loop, a current source is provided, which additionally feeds current into the regulating loop and thereby ensures that a control voltage for the load does not fall below a predetermined value.

Abstract: The present invention is related to an analog/digital converter which includes a multitude of integrating circuits, a 1 bit analog/digital converter and a 1 bit digital/analog converter. The multitude of analog integrating circuits are connected in series and the 1 bit digital/analog converter is connected downstream from the last analog integrating circuit of the series. An output signal of the 1 bit analog/digital converter is transmitted to the 1 bit digital/analog converter, and an output signal of the 1 bit digital/analog converter is subtracted from an input signal of each analog integrating circuit. A multitude of input signals is transmitted via a multiplexer to the first analog integrating circuit of the series-connected analog integrating circuits.