Abstract: A semiconductor memory chip in which signals are transferred as serial signal frames includes a frame decoder providing an interface between a memory core and a reception interface. The frame decoder includes a command type decoder for decoding the types of commands included in frames according to the decoded type of the commands, a memory command evaluator/generator for scheduling and preparing single commands for the core, an intermediate data buffer command evaluator/generator for scheduling and preparing control signals for an intermediate data buffer, and a system command evaluator/generator for preparing and scheduling system commands. These system commands provide timing parameters to ensure time intervals between consecutive commands within one frame or between frames and are stored in a system mode register. The operation of the frame decoder is edge-synchronized by a frame clock or a synchronization decoder clock signal which is phase-aligned to that frame clock signal.

Abstract: A semiconductor memory chip includes: a reception interface section for receiving external data, command, and address signals in form of serial signal frames; an intermediate data buffer for intermediately storing write data and, optionally, write data mask bits to be written to a memory cell array; a memory core having a bank organized memory cell array; a decoder section for decoding an address derived from a signal frame received from the reception interface section for writing/reading data in/from one or more memory banks of the memory cell array in accordance with a write/read command within one or more received signal frames; and a frame decoder provided as an interface between the reception interface section and the memory core for decoding one or more commands included in one or more frames and outputting data addresses, command, and read/write access indication signals to the memory core and to the intermediate data buffer.

Abstract: A method for transferring data into a data memory using a data protocol is presented. The data memory is an error correction code (ECC) memory or a non-error correction code memory. The data protocol has different frames. When data are written into an ECC memory, the protocol includes a data mask frame in which the data mask bits are replaced by ECC bits. The method is designed such that ECC and non-ECC DRAMs can be established with the same protocol and at least a similar architecture.

Abstract: One embodiment of the present invention provides to a memory device adapted to receive data according to a write clock signal and to output data according to a read clock signal, comprising a clock port configured to output the read clock signal and to receive the write clock signal and a serial bidirectional driver configured to output the read clock signal via the clock port and to receive the write clock signal via the clock port simultaneously.

Abstract: A semiconductor memory device includes semiconductor memory cells with at least one memory cell capable of acting either in a first mode, wherein it functions as a storage device for ECC information, or in a second mode, wherein it functions as either as a redundant memory cell or a as a cell storing ordinary information. The semiconductor memory device further includes a signal control device for signaling if the at least one memory cell is to be used either in the first mode or in the second mode. A method of operating a semiconductor memory device is also provided including the steps of registering a status of a signal device and, depending on the status of the signal device, operating the at least one memory cell either in the first mode or in either of the selected second modes.

Abstract: The present invention relates to a memory system having a memory device with two clock lines. One embodiment of the present invention provides a memory system comprising at least one memory device, a memory controller to control operation of the memory device, a first clock line which extends from a write clock output of the memory controller to a clock port of the memory device to provide a clock signal to the memory device, and a second clock line which extends from the clock port of the memory device to a read clock input of the memory controller to forward the clock signal applied to the clock port of the memory device back to a read clock input of the memory controller. The memory device may further comprise a synchronization circuit adapted to receive the clock signal from the memory controller and to, provide an output data synchronized to the forwarded clock signal.

Abstract: A semiconductor memory device comprises a temperature dependent voltage source for outputting a voltage at its output in dependence on a temperature measured in the semiconductor memory device. At least one memory cell is provided with at least one first transistor. The first transistor includes a first transistor body, which is connected to the output of said temperature dependent voltage source.

Abstract: One embodiment of the present invention provides a memory device comprising a plurality of sets of memory banks, wherein each memory bank includes a memory array and is adapted to be read out in a data access; a plurality of internal data buses and a plurality of internal command and address buses connected to the plurality of sets of memory banks, respectively, such that each set of memory banks is associated with one of the internal data buses and one of the internal command and address buses; a command and address port for receiving command and address data from outside; and a command and address unit to direct the received command and address data to one of the sets of memory banks via the associated command and address bus, depending on the address data; and a data output unit for receiving data read out from one set of memory banks via the respective internal data bus in the data access and for serially outputting the received data.

Abstract: A semiconductor memory module includes a plurality of semiconductor memory chips and bus signal lines that supply an incoming clock signal and incoming command and address signals to the semiconductor memory chips. A clock signal regeneration circuit and a register circuit are arranged on the semiconductor memory module in a common chip packing connected to the bus signal lines. The clock signal regeneration circuit and the register circuit respectively condition the incoming clock signal and temporarily store the incoming command and address signals, respectively multiply the conditioned clock signal and the temporarily stored command and address signals by a factor of 1:X, and respectively supply to the semiconductor memory chips the conditioned clock signal and the temporarily stored command and address signals.

Abstract: The present invention relates to an integrated memory device including: memory cells arranged at wordlines and bitlines, wherein the memory cells are addressable in sets of 2n bit, wherein n is an integer, a pre-fetch read unit to pre-fetch an addressed set of 2n data bit in parallel from the addressed memory area, buffer memory to buffer the number of pre-fetched data bits; a number m of output ports to output the data bits buffered in the buffer memory; an output controller for controlling the outputting of the data bits buffered in the buffer memory to the number m of output ports in groups of m bits in one or a plurality of successive cycles, characterized in that the number m of output ports is different to any of the possible numbers 2n of the sets of addressable memory cells.

Abstract: A semiconductor memory system for the transfer of write and read data signals among interface circuits includes at least one memory device, a memory controller unit and, optionally, a register unit of a semiconductor memory system, wherein the data signals are each transferred in signal bursts of a specific burst length. The system is characterized in that a number of additional bits extending the burst length are transferred together with at least every nth signal burst.

Abstract: A semiconductor memory system for the transfer of write and read data signals among interface circuits includes at least one memory device, a memory controller unit and, optionally, a register unit of a semiconductor memory system, wherein the data signals are each transferred in signal bursts of a specific burst length. The system is characterized in that a number of additional bits extending the burst length are transferred together with at least every nth signal burst.

Abstract: A semiconductor memory module includes a plurality of semiconductor memory chips. Each semiconductor memory chip includes an interface circuit that is configured to detect a transmission error in a write datum and is further configured to output, via a separate signal path, a repeat request signal for the repeated transmission of the write datum detected as erroneous. This repeat request signal can be transmitted either as a single-bit signal or as a multibit signal (e.g., serially as an individual signal line to a superordinate memory controller).

Abstract: One embodiment of the present invention provides to a memory device adapted to receive data according to a write clock signal and to output data according to a read clock signal, comprising a clock port configured to output the read clock signal and to receive the write clock signal and a serial bidirectional driver configured to output the read clock signal via the clock port and to receive the write clock signal via the clock port simultaneously.

Abstract: The present invention relates to a memory system having a memory device with two clock lines. One embodiment of the present invention provides a memory system comprising at least one memory device, a memory controller to control operation of the memory device, a first clock line which extends from a write clock output of the memory controller to a clock port of the memory device to provide a clock signal to the memory device, and a second clock line which extends from the clock port of the memory device to a read clock input of the memory controller to forward the clock signal applied to the clock port of the memory device back to a read clock input of the memory controller. The memory device may further comprise a synchronization circuit adapted to receive the clock signal from the memory controller and to, provide an output data synchronized to the forwarded clock signal.

Abstract: An integrated circuit has a first voltage generator, which is connected via a first switching element to a contact-making point for external contact making with the circuit. In addition, it has a first digital control device, via which the contact-making point is connected to a control input of the first switching element. In this case, the first control device switches the first switching element on or turns the latter off by a first digital control signal, the level of which is dependent on the potential of the contact-making point. Furthermore, the contact-making point is connected to the input of a second digital control device, which supplies a digital operating mode signal at its output, the level of which operating mode signal is dependent on the potential of the contact-making point.

Abstract: An integrated circuit includes a voltage regulator for generating an internal supply voltage. The voltage regulator has one input for applying an actual value and one input for applying a reference voltage as a desired value. The actual value is generated through the use of a first voltage divider from the internal supply voltage. A sensitivity of the voltage regulator is dependent on a resistance of at least one resistor element of the first voltage divider. A second voltage divider, which is connected parallel to the first voltage divider, has the same voltage divider ratio as the first voltage divider and is activatable and deactivatable by at least one switch element.

Abstract: A circuit configuration for reducing disturbances due to a switching of an output driver. The output driver has a plurality of output driver stages and a delay element. The delay element increases the signal delay of the switch-on or switch-off signals for the output driver stages with an increasing supply voltage.

Abstract: The device for generating digital signal levels can be used for signals of various logic standards. A voltage terminal for feeding an external reference voltage is provided as well as an internal voltage generator. An internal reference voltage of the voltage generator can be selectively connected to the device via a switch. The switch is actuated by a level converter. Coupling elements prevent faults caused by the supply voltage.

Abstract: The input amplifier with unilateral current shutoff for input signals with steep edges has a MOS transistor, the source or drain of which is connected to a node connected to an output stage. An N-channel MOS transistor, which is connected between the two P-channel MOS transistors of the input amplifier, prevents a shutoff of the P-channel MOS transistor by the steep edge input signals. The node is pulled upward to the operating voltage when the input signal is present.