Abstract: A method including receiving, at a server, vessel AIS information, said AIS information including at least a vessel identifier and a vessel location. Querying a location data store in response to the vessel location, said location data store including port location information. Determining, in response to said querying, whether the vessel is in a port area or port approach area and iteratively receiving, additional AIS information which may be stored as structured data. And calculating port performance metrics in response to the location information, and transmitting those performance metrics through a network.

Abstract: A method including receiving, at a server, vessel AIS information, said AIS information including at least a vessel identifier and a vessel location. Querying a location data store in response to the vessel location, said location data store including port location information. Determining, in response to said querying, whether the vessel is in a port area or port approach area and iteratively receiving, additional AIS information which may be stored as structured data. And calculating port performance metrics in response to the location information, and transmitting those performance metrics through a network.

Abstract: The present invention provides new energy solutions that are sustainable both environmentally and economically. The invention relates to photo-biocatalytic (PBC) methods and systems designed to produce and isolate carbonaceous chemicals using carbon dioxide, sunlight, and genetically engineered photosynthetic microorganisms. The PBC system comprises of procedural, mechanical and biological components designed for the production of carbonaceous chemicals.

Abstract: A component with a logic circuit arrangement with configurable functionality, includes several data lines (7), whereby at least a part of the data lines (7) is provided with at least one element (1) which may be switched between two states with different discrete resistances. The data line (7) is opened or closed by the element (1), depending on the switched state.

Abstract: A component with a functionally-configurable circuit arrangement, has a first switch group with a voltage-dependent switching on or off of a data line and at least one second switch group generating two discrete output voltages separated by an increase in voltage and the switch states for the discrete output voltages may be stored in non-volatile memory. The switching on or off of the data line is determined by the switch state of the first switch group and a third switch group (11) is provided to increase the voltage increase between the first switch group (17) and the second switch group (3).

Abstract: A component with a functionally-configurable circuit arrangement, has a first switch group with a voltage-dependent switching on or off of a data line and at least one second switch group generating two discrete output voltages separated by an increase in voltage and the switch states for the discrete output voltages may be stored in non-volatile memory. The switching on or off of the data line is determined by the switch state of the first switch group and a third switch group (11) is provided to increase the voltage increase between the first switch group (17) and the second switch group (3).

Abstract: The invention relates to a computer containing a RAM-based primary part (Ht) with a stucturable RAM unit (2). On the input side, a first crossbar switch (1) is located upstream of said unit and a second crossbar switch (3) is located downstream. Address signals (18, 13) can be supplied from the first crossbar switch (1) to the RAN unit (2) or the second crossbar switch (3). Output signals (10) can be fed back from the second crossbar switch to the first crossbar switch (1) and can be output. An additional control part (St) for a configurable job sequencing of the primary part (Ht) comprises a counter unit (4) that is synchronised with the first crossbar switch (1) to create counter reading signals (12) for the first and second crossbar switch (1 and 3). The computer is particularly suitable for integrating a global cellular automaton (GCA).

Abstract: A configurable logic circuit arrangement includes at least one multiplexer for switching logic signals. The multiplexer includes one or more data inputs and one or more control signal inputs. The at least one multiplexer (8, 12, 13) can be configured by one or more external control signal transmitter elements of the circuit arrangement during the operation of the circuit in a run-time variable manner by configuration signals that are applied to the control inputs and forwards the logical signals that are applied to the data inputs during operation of the circuit in a run-time variable manner.

Abstract: A configurable architecture of a calculation device includes at least one individual configurable and/or reconfigurable switching device, whereby the output variables thereof form a time point tn-1 and the input variables of the switching device form a time point tn. Elements are provided in order to control the output variables in a clocked manner and to store the output variables of the switching device between the time points tn-1 and tn.

Abstract: A computer containing a RAM-based primary part (Ht) with a stucturable RAM unit (2). On the input side, a first crossbar switch (1) is located upstream of the unit and a second crossbar switch (3) is located downstream. Address signals (18, 13) can be supplied from the first crossbar switch (1) to the RAM unit (2) or the second crossbar switch (3). Output signals (10) can be fed back from the second crossbar switch to the first crossbar switch (1) and can be output. An additional control part (St) for a configurable job sequencing of the primary part (Ht) comprises a counter unit (4) that is synchronized with the first crossbar switch (1) to create counter reading signals (12) for the first and second crossbar switch (1 and 3). The computer is particularly suitable for integrating a global cellular automaton (GCA).

Abstract: A configurable architecture of a calculation device includes at least one individual configurable and/or reconfigurable switching device, whereby the output variables thereof form a time point tn-1 and the input variables of the switching device form a time point tn. Elements are provided in order to control the output variables in a clocked manner and to store the output variables of the switching device between the time points tn-1 and tn.

Abstract: A component with a logic circuit arrangement with configurable functionality, includes several data lines (7), whereby at least a part of the data lines (7) is provided with at least one element (1) which may be switched between two states with different discrete resistances. The data line (7) is opened or closed by the element (1), depending on the switched state.

Abstract: A configurable logic circuit arrangement includes at least one multiplexer for switching logic signals. The multiplexer includes one or more data inputs and one or more control signal inputs. The at least one multiplexer (8, 12, 13) can be configured by one or more external control signal transmitter elements of the circuit arrangement during the operation of the circuit in a run-time variable manner by configuration signals that are applied to the control inputs and forwards the logical signals that are applied to the data inputs during operation of the circuit in a run-time variable manner.

Abstract: The invention relates to a programmable logic device (7) comprising several logic blocks (3A to 3D) with configurable characteristics, elements for linking the logic blocks to one another and a processing unit (4) and an input/output unit (5). In addition, the linking elements have at least one configurable changeover logic block, enabling the logic blocks (3A to 3D) to be re-configured during the operation of the logic device (7). Said changeover logic block is used for the configuration of at least one of the re-configurable logic blocks (3A to 3D) and its connection to other blocks and/or its connection to the processing unit (4) and/or to the input/output unit (5).

Abstract: The configurable hardware block is designed to read data stored in a memory according to its configuration, to process the read-out data arithmetically and/or logically and to write the data representing the result of the processing into the memory. The hardware block is capable of interacting with external hardware, thereby providing a flexible and universally applicable hardware block.

Abstract: A programmable logic device (7) includes several logic blocks (3A to 3D) with configurable characteristics, elements for linking the logic blocks to one another and a processing unit (4) and an input/output unit (5). In addition, the linking elements have at least one configurable changeover logic block, enabling the logic blocks (3A to 3D) to be re-configured during the operation of the logic device (7). The changeover logic block is used for the configuration of at least one of the re-configurable logic blocks (3A to 3D) and its connection to other blocks and/or its connection to the processing unit (4) and/or to the input/output unit (5).

Abstract: A method for configuring a configurable hardware block includes implementing commands and/or command sequences of a program to be executed. The implementing step includes ascertaining a given type of subunit of a configurable hardware block, the given type of subunit being required for executing a respective command, selecting, if available, a subunit of the given type of subunit, configuring configurable connections provided around the subunit selected in the selecting step, if the subunit of the given type of subunit is found in the selecting step, and ascertaining configuration data with the step of implementing the commands and/or command sequences. The configurable hardware block is configured by using the configuration data.

Abstract: The configurable hardware block is designed to read data stored in a memory according to its configuration, to process the read-out data arithmetically and/or logically and to write the data representing the result of the processing into the memory. The hardware block is capable of interacting with external hardware, thereby providing a flexible and universally applicable hardware block.

Abstract: A self testable communications device (102) such as a cable modem, a system (100) of remotely distributed such devices (102) and the method (140) of testing. One or more cable modems (102) are connected to a distribution hub (110). Each cable modem (102) includes a connection test initiator, such as a button (130) on the cable modem (102), on a web page or, on a computer (104) desk top which is accessible from the particular cable modem (102). When a test (140) is initiated by pressing or selecting the button (130), the system (100) initiates diagnostics (140) to check the connection of the cable modem (102) to the distribution hub (110). After the test (140) is complete, the cable modem user is provided with an automatic response indicating connection test (140) results.

Abstract: A method for configuring a configurable hardware block includes implementing commands and/or command sequences of a program to be executed. The implementing step includes ascertaining a given type of subunit of a configurable hardware block, the given type of subunit being required for executing a respective command, selecting, if available, a subunit of the given type of subunit, configuring configurable connections provided around the subunit selected in the selecting step, if the subunit of the given type of subunit is found in the selecting step, and ascertaining configuration data with the step of implementing the commands and/or command sequences. The configurable hardware block is configured by using the configuration data.