Abstract: A chip component (1) includes a semiconductor body (2), in which at least one switchable element (6, 62) is arranged in a partial region (24) of the semiconductor body (2). The partial region (24) can be reached by light of at least one wavelength. Furthermore, a circuit (9) integrated into the semiconductor body (2) is provided, which integrated circuit can assume one configuration from at least two possible configurations, one of these configurations being prescribed by a state of the at least one switchable element (6, 62). Furthermore, a housing (3) is provided, which encloses the semiconductor body (2) and is arranged with a partial region (35, 32) at least partly above the partial region (24) of the semiconductor body (2). The partial region (35, 32) of the housing (3) is formed in such a way that light can be fed to the partial region (24) of the semiconductor body (2).

Abstract: An integrated semiconductor memory device includes a first memory zone, a second memory zone, first address connections and a second address connection. A second address signal present at the second address connection specifies the access to the first or second memory zone, whereas it is specified via first address signals at the first address connections which memory cell is accessed within the first or second memory zone. In a first memory configuration, all address connections are driven externally with address signals and the access to a memory cell in the first or second memory zone is controlled. In a second memory configuration, only the first address connections are driven externally whereas a signaling bit in a mode register regulates the access to the first or second memory zone. This provides for access to the second memory zone even if there is no possibility of externally driving the second address connection.

Abstract: A test method for a semiconductor memory device having a bidirectional data strobe terminal for a data strobe signal, and having at least one data terminal for a data signal at a test apparatus, which can at least generate data strobe and data signals and also transfer and evaluate data signals. The memory device is connected to a test apparatus, which generates data strobe and data signals, and transfers and evaluates data signals. In the course of the test using the data strobe and data signals, data are transferred from the first semiconductor memory device to a second semiconductor memory device of identical type and are evaluated after a read-out from the second semiconductor memory device by the test apparatus.

Abstract: A test arrangement with a test memory chip and a control device is provided. Error correction data are stored in the test memory chip with the aid of the control device. In the case of an error event, it is ascertained whether the error occurred on the error correction chip. If so, the memory controller compares the data stored in the error correction chip with the data of the auxiliary memory. The address of the error correction chip can be deduced from the address of the auxiliary memory, thereby enabling unambiguous addressing of a defective memory cell of the error correction chip.

Abstract: A memory module includes at least one memory chip arranged on the memory module. Information about the memory module and/or the at least one memory chip arranged on the memory module can be stored directly on the memory chip, making use of a suited element, fuses or flip-flops, for example. A memory chip contains such an element for containing information relating to the memory chip and/or a memory module with which the memory chip is compatible, wherein the information containing element can be read out by means of an external processor.

Abstract: A semiconductor device testing apparatus, system, and method, in particular for testing the contacting with semiconductor devices positioned one upon the other, wherein at least two semiconductor devices are provided that are connected to a device module, at least one pin of a first semiconductor device is conductively connected with a pad, and at least one pin of a second semiconductor device also is to conductively connected with the pad. A first value is written into a memory cell of the first semiconductor device, a second value differing from the first value is written into a memory cell of the second semiconductor device, and a signal corresponding to the first value at the pin of the first semiconductor device and of a signal corresponding to the second value at the pin of the second semiconductor device is simultaneously output.

Abstract: A circuit arrangement can have a number of integrated circuit components, which are arranged on a carrier substrate. A reception circuit for receiving a control signal can be coupled to one of the connection pads on the input side and can be connected to each of the circuit components on the output side. A bridging circuit controlled by a test mode signal can electrically bridge the reception circuit. In a testing method, a plurality of connection pads can be connected to a first potential and at least one of the connection pads can be connected to a second potential. The bridging circuit can be activated and the current measured, by a test arrangement, at the at least one of the connection pads. Inspection for leakage currents in connections between input-side reception circuits and the circuit components can be measured.

Abstract: An apparatus (1) for testing a memory module (2) suitable for exchanging electrical signals with a motherboard (10) contains a device (8a–8k) suitable for detecting the operating state of at least one semiconductor chip (26a–26m) of the module, which device comprises a first set of signal lines (8a–8k), a microcontroller (3) with a memory device (32) for storing the operating state, said microcontroller being electrically connected to the signal lines (8a–8k), a clock generator (5) suitable for generating an operating clock, said clock generator being electrically connected to the microcontroller (3), and a signal connection (13) suitable for communicating a signal for controlling access to the memory module (2) between the circuit board arrangement (10) and the microcontroller (3) and for communicating to the microcontroller (3) a signal for initiating a process of detecting the operating state.

Abstract: An integrated semiconductor memory device includes a first memory zone, a second memory zone, first address connections and a second address connection. A second address signal present at the second address connection specifies the access to the first or second memory zone, whereas it is specified via first address signals at the first address connections which memory cell is accessed within the first or second memory zone. In a first memory configuration, all address connections are driven externally with address signals and the access to a memory cell in the first or second memory zone is controlled. In a second memory configuration, only the first address connections are driven externally whereas a signaling bit in a mode register regulates the access to the first or second memory zone. This provides for access to the second memory zone even if there is no possibility of externally driving the second address connection.

Abstract: A memory circuit includes a plurality of memory cells, an input/output area for addressing or writing onto the plurality of memory cells by means of electrical signals, and an optical-electrical converter for converting optical signals into the electrical signals, the plurality of memory cells and the input/output area being integrated on a chip, and the optical-electrical converter being mechanically connected to the chip or being integrated into the chip.

Abstract: An error code is generated by generating error correction data from a data sequence. These error correction data together with the data sequence are then written to a memory unit so as to be read from the memory unit. During the reading or during the writing, one bit in the data sequence has its content changed. This induces a bit error from which an error code is generated which can be clearly associated with the bit error. An interface arrangement can be inserted between a computer and a memory module. The interface arrangement contains data lines that are coupled to an apparatus which is designed to generate bit errors during a write or read operation.

Abstract: A chip component (1) includes a semiconductor body (2), in which at least one switchable element (6, 62) is arranged in a partial region (24) of the semiconductor body (2). The partial region (24) can be reached by light of at least one wavelength. Furthermore, a circuit (9) integrated into the semiconductor body (2) is provided, which integrated circuit can assume one configuration from at least two possible configurations, one of these configurations being prescribed by a state of the at least one switchable element (6, 62). Furthermore, a housing (3) is provided, which encloses the semiconductor body (2) and is arranged with a partial region (35, 32) at least partly above the partial region (24) of the semiconductor body (2). The partial region (35, 32) of the housing (3) is formed in such a way that light can be fed to the partial region (24) of the semiconductor body (2).

Abstract: A housing, in particular for semiconductor devices, a semiconductor device pin, and a method for the manufacturing of pins wherein at least one pin is punched out from a basic body, in particular a lead framed, by means of one or a plurality of punching process steps, wherein the pin is coated with a separate metal layer after the final punching out of said pin.

Abstract: A device for cooling memory modules can include a plurality of elements. The elements can thermal couple at least two memory modules. The device can further include a body or a plurality of contact areas bearing in a planar manner.

Abstract: A test arrangement with a test memory chip and a control device is provided, which has a first and a second interface. The test arrangement is connected to a memory slot of a computer system and is connected by its second interface to a memory module. Error correction data that are written to the error correction chip of the memory module by a memory controller of the computer system are stored in the test memory chip with the aid of the control device. In the case of an error event, it is ascertained whether the error occurred on the error correction chip. If this is the case, the memory controller compares the data stored in the error correction chip with the data of the auxiliary memory. The address of the error correction chip can be deduced from the address of the auxiliary memory, thereby enabling unambiguous addressing of a defective memory cell of the error correction chip.

Abstract: An apparatus (1) for testing a memory module (2) suitable for exchanging electrical signals with a motherboard (10) contains a device (8a-8k) suitable for detecting the operating state of at least one semiconductor chip (26a-26m) of the module, which device comprises a first set of signal lines (8a-8k), a microcontroller (3) with a memory device (32) for storing the operating state, said microcontroller being electrically connected to the signal lines (8a-8k), a clock generator (5) suitable for generating an operating clock, said clock generator being electrically connected to the microcontroller (3), and a signal connection (13) suitable for communicating a signal for controlling access to the memory module (2) between the circuit board arrangement (10) and the microcontroller (3) and for communicating to the microcontroller (3) a signal for initiating a process of detecting the operating state.

Abstract: A test method for a semiconductor memory device having a bidirectional data strobe terminal for a data strobe signal, and having at least one data terminal for a data signal at a test apparatus, which can at least generate data strobe and data signals and also transfer and evaluate data signals. The memory device is connected to a test apparatus, which generates data strobe and data signals, and transfers and evaluates data signals. In the course of the test using the data strobe and data signals, data are transferred from the first semiconductor memory device to a second semiconductor memory device of identical type and are evaluated after a read-out from the second semiconductor memory device by the test apparatus.

Abstract: A device for cooling memory modules can include a plurality of elements. The elements can thermal couple at least two memory modules. The device can further include a body or a plurality of contact areas bearing in a planar manner.

Abstract: A semiconductor device testing apparatus, system, and method, in particular for testing the contacting with semiconductor devices positioned one upon the other, wherein at least two semiconductor devices are provided that are connected to a device module, at least one pin of a first semiconductor device is conductively connected with a pad, and at least one pin of a second semiconductor device also is to conductively connected with the pad. A first value is written into a memory cell of the first semiconductor device, a second value differing from the first value is written into a memory cell of the second semiconductor device, and a signal corresponding to the first value at the pin of the first semiconductor device and of a signal corresponding to the second value at the pin of the second semiconductor device is simultaneously output.

Abstract: A housing, in particular for semiconductor devices, a semiconductor device pin, and a method for the manufacturing of pins wherein at least one pin is punched out from a basic body, in particular a lead framed, by means of one or a plurality of punching process steps, wherein the pin is coated with a separate metal layer after the final punching out of said pin.