Abstract: A method for producing a sealing arrangement between an opening of the support, bore and a screw which comprises a head connected to a body and is provided with a threaded section for interacting with the hole of a part to be assembled with a support whose mechanical strength is lower than that of the screw. The invention is characterized in that, starting from an enlarged opening, the inventive method consists in engaging the screw into the bore in such a way that the head thereof is brought into contact with the opening, in screwing the screw into the hole of the part to be assembled in such a way that a pressure applied by the head sealingly presses the opening against the part of the under-head surface of the screw by removing a part of material of the support.

Abstract: A method for producing a sealing arrangement between an opening of the support, bore and a screw which comprises a head connected to a body and is provided with a threaded section for interacting with the hole of a part to be assembled with a support whose mechanical strength is lower than that of the screw. The invention is characterized in that, starting from an enlarged opening, the inventive method consists in engaging the screw into the bore in such a way that the head thereof is brought into contact with the opening, in screwing the screw into the hole of the part to be assembled in such a way that a pressure applied by the head sealingly presses the opening against the part of the under-head surface of the screw by removing a part of material of the support.

Abstract: A routing device is provided for transporting digital data from demodulated digital television signals. The routing device includes a network that routes the digital data to demultiplexers via at least one decoding module. The network includes means for connecting to at least two independent demodulation channels, with each of the demodulation channels producing digital data from a demodulator. The network allows individual routing of the digital data from each of the demodulation channels to the demultiplexers via at least one decoding module. Also provided are a corresponding routing method and a host device that includes such a routing device. Exemplary applications of the routing device and method are a digital television receiver with an image incorporation (picture in picture) function, and a digital television combined with a recording device.

Abstract: A routing device is provided for transporting digital data from demodulated digital television signals. The routing device includes a network that routes the digital data to demultiplexers via at least one decoding module. The network includes means for connecting to at least two independent demodulation channels, with each of the demodulation channels producing digital data from a demodulator. The network allows individual routing of the digital data from each of the demodulation channels to the demultiplexers via at least one decoding module. Also provided are a corresponding routing method and a host device that includes such a routing device. Exemplary applications of the routing device and method are a digital television receiver with an image incorporation (picture in picture) function, and a digital television combined with a recording device.

Abstract: The process for coding characters and associated display attributes in a video system consists in: coding a first cue of character type in a first word; coding a second cue of display attribute type, a so-called parallel attribute, defining the color or aspect associated with a character, in a second word, comprising at least one selection bit whose value indicates whether the parallel display attribute transmitted is a color attribute or a shape attribute; storing the value of the said parallel display attribute; using, for display of the current character, the color attribute, respectively the shape attribute, transmitted at the same time as the current character, or by default, the color attribute, respectively the shape attribute, stored during transmission of a previous character.

Abstract: In a device for controlling the displaying of characters for a video system, the memory for storing information relating to the displaying of the characters is partitioned into two areas. The first area (Z1, Z1′) is for storing, at fixed addresses, data and parameters for general control of the display. The second area (Z2) which is divisible into spaces (B1, B2, B3) of variable sizes stores, in each of the spaces, control parameters and data relating to the displaying of a row of characters, wherein the spaces are chained together by virtue of a parameter, the address of the next memory space, stored in each space. This memory architecture offers multiple possibilities for modifying the display parameters from one row to another within one and the same “screen” whilst optimizig the size of the memory used.

Abstract: Several peripheral entities, each of which is clocked by its own internal clock signal, can access a memory that is a single-access memory. A priority entity is defined from among the peripheral entities, and the other entities are defined as auxiliary entities. A repetitive time frame is formulated so as to be regulated by the internal clock signal of the priority entity. This time frame is subdivided into several groups of windows that are allocated to the peripheral entities. Each peripheral entity can access the memory only during the windows that are allocated to that entity.

Abstract: Several peripheral entities are provided, with each peripheral entity being clocked by its own internal clock signal and being able to access a single-access memory. A priority entity is defined from among the peripheral entities, and the other peripheral entities are defined as auxiliary entities. A repetitive time frame is formulated, regulated by the internal clock signal of the priority entity, and subdivided into several groups of time windows that are allocated to the peripheral entities. One of the peripheral entities is a microprocessor that is disabled for a fixed duration after each memory access request.

Abstract: The process for coding characters and associated display attributes in a video system consists in:

Abstract: Several peripheral entities are provided, with each peripheral entity being clocked by its own internal clock signal and being able to access a single-access memory. A priority entity is defined from among the peripheral entities, and the other peripheral entities are defined as auxiliary entities. A repetitive time frame is formulated, regulated by the internal clock signal of the priority entity, and subdivided into several groups of time windows that are allocated to the peripheral entities. One of the peripheral entities is a microprocessor that is disabled for a fixed duration after each memory access request.

Abstract: Several peripheral entities, each of which is clocked by its own internal clock signal, can access a memory that is a single-access memory. A priority entity is defined from among the peripheral entities, and the other entities are defined as auxiliary entities. A repetitive time frame is formulated so as to be regulated by the internal clock signal of the priority entity. This time frame is subdivided into several groups of windows that are allocated to the peripheral entities. Each peripheral entity can access the memory only during the windows that are allocated to that entity.

Abstract: The memory (MM) is addressed, depending on the format, with address words (MDC) formed at least from the high-order bits of the identifier (ID) of each cue, and possibly padded out with check or selection words (MS) making it possible either to designate consecutive addresses or to select some of the latter from each memory cell (CM) depending on the low-order bits of the identifier. This allows continuous addressing of the memory irrespective of the format used, thereby optimizing the memory size and avoiding a structural or software modification of the addressing system with each change of format.

Abstract: Method and device for correcting errors in synchronization of operations of recovering sequences of ancillary data transmitted over the invisible lines of the VBI of a video signal including a vertical synchronization signal Vsync and a horizontal synchronization signal Hsync used to synchronize the opening of time windows for recovery of the data. In the event of the absence of a horizontal synchronization pulse at the end of a period equal to H+.DELTA.H, where H is the period of the signal Hsync and .DELTA.H is a first predetermined lapse of time, an artificial synchronization pulse is generated, and the moment of opening of the window for recovering ancillary data to the moment of generation of the artificial synchronization pulses so as to cause the moment to coincide with the start of the sequence of ancillary data to be recovered.

Abstract: A device including a mechanism (4) for generating a counting clock signal (CKM) whose frequency is less than or equal to n times twice the transmission frequency. The device also includes a detection mechanism (10) for detecting the transitions (TD) of the signal (DS) at the counting frequency and for delivering corresponding detection signals (ST), a selection mechanism (2) for receiving each detection signal (ST) and for delivering or otherwise a selection signal (RS) depending on the satisfying or otherwise of a predetermined selection criterion, and a frequency divider-by-n (30) which receives the counting clock signal, in order to sample the carrier signal after a predetermined time delay (Tr) after each detected transition. Provided are a sampling control device and method which are completely digital and therefore use no analog component of the phase-locked loop type and are very simple to produce at an industrially economical cost.

Abstract: The present invention relates to a buffer for logic signals including a MOS output transistor of a first conductivity type connected by its source to a first supply potential, the drain of this transistor forming an output terminal of the buffer; a control transistor for controlling the output transistor connected between the gate of the output transistor and a second supply potential; a third transistor of the first conductivity type connected between the gate of the output transistor and the first supply potential and controlled to maintain the gate-source voltage of the buffer close to a threshold voltage so that the output transistor operates as a current generator; and a fourth transistor connected to render floating the gate of the third transistor when the potential on the output terminal is close to the first supply potential.

Abstract: The invention relates to remotely powered circuitry, and in particular to telephones. The circuit of the invention uses a counter to measure or compare the duration of power supply interruptions on the remote power supplying line to cause the remotely powered circuitry to be initialized whenever the duration of such an interruption becomes greater than or less than a specified duration. Advantageously, comparators are used so as to be able to take a plurality of durations into consideration. Thus, each time the power supply on the remote power line is interrupted, if the interruption is not of an acceptable duration, then the remotely powered circuitry is initialized.

Abstract: A CMOS integrated circuit incorporating both logic functions and analog functions. The latter are subjected to noise from the logic transitions by means of supply conductors. To avoid disturbing the rest point of an amplifier by this supply noise, without using compensation circuits which would increase the number of pins of the integrated circuit, it is proposed to supply a pair of complementary transistors forming an amplifier stage by identical incoming and outgoing current generators. These generators are transistors copying a current from a current mirror circuit which includes a pair of complementary transistors connected between the two power supply lines.