Abstract: Performing a Fast Fourier Transformation (FFT) with increased resolution by applying an adaptive left shift to signed binary integers of an input of a radix kernel and adaptive right shift to signed binary integers of an output of a butterfly of the radix kernel which is based on a leading bit count of the input. The adaptive left shift increases a resolution of the radix kernel computation and the adaptive right shift determines a number of bits of the increased resolution preserved in an output of the radix kernel.

Abstract: Aspects of the present disclosure relate to a radar system and method of operation thereof, whereby a spectrogram is generated by processing circuitry of a radar system by converting samples, of reflections of transmitted radar signals reflected by an object in an environment of the radar system, into a time-frequency domain, determining at least one threshold based on at least one MIN-of-MAX value for magnitudes of a frequency signal of the spectrogram, generating an interference-suppressed spectrogram by removing or attenuating interference components from the spectrogram based on the at least one threshold, and generating interference-suppressed samples based on the interference-suppressed spectrogram.

Abstract: A processing system including a memory, command sequencers, accelerators, and memory banks. The memory stores program code including instruction threads sequentially listed in the program code. The command sequencers include a master command sequencer and multiple slave command sequencers. The master command sequencer executes the program code including distributing the instruction threads for parallel execution among the slave command sequencers. The instruction threads may be provided inline or accessed via inline thread line pointers. Each accelerator is available to each command sequencer in which multiple command sequencers may access multiple accelerators for parallel execution. The memory banks are simultaneously available to multiple accelerators. The master command sequencer may perform implicit synchronization by waiting for completion of simultaneous execution of multiple instruction threads. A command sequencer arbiter may arbitrate among the command sequencers.

Abstract: A method and circuit for a data processing system provide a hardware accelerator repeat control instruction (402A) which is executed with a hardware accelerator instruction (402B) to extract and latch repeat parameters from the hardware accelerator repeat control instruction, such as a repeat count value (RPT_CNT), a source address offset value (ADDR_INCR0), and a destination address offset value (ADDR_INCR1), and to generate a command to the hardware accelerator (205) to execute the hardware accelerator instruction a specified plurality of times based on instruction parameters from the hardware accelerator instruction by using the repeat count value to track how many times the hardware accelerator instruction is executed and by automatically generating, at each execution of the hardware accelerator instruction, additional source and destination addresses for the hardware accelerator from the repeat parameters until the hardware accelerator instruction has been executed the specified plurality of times by the

Abstract: A processing system including a memory, command sequencers, accelerators, and memory banks. The memory stores program code including instruction threads sequentially listed in the program code. The command sequencers include a master command sequencer and multiple slave command sequencers. The master command sequencer executes the program code including distributing the instruction threads for parallel execution among the slave command sequencers. The instruction threads may be provided inline or accessed via inline thread line pointers. Each accelerator is available to each command sequencer in which multiple command sequencers may access multiple accelerators for parallel execution. The memory banks are simultaneously available to multiple accelerators. The master command sequencer may perform implicit synchronization by waiting for completion of simultaneous execution of multiple instruction threads. A command sequencer arbiter may arbitrate among the command sequencers.

Abstract: A method and apparatus for handling outstanding interconnect transactions between a master device and an interconnect component. For example, a transaction intervention module coupled to an interconnect component and a master device of the interconnect component. The transaction intervention module is arranged to receive an indication of a functional state of the master device. If the master device is indicated as being in a faulty functional state the transaction intervention module is further arranged to determine whether any interconnect transactions initiated by the master device with the interconnect component are outstanding. If it is determined that at least one interconnect transaction initiated by the master device is outstanding, the transaction intervention module is arranged to finalize the at least one outstanding interconnect transaction with the interconnect component.

Abstract: A method and apparatus for handling outstanding interconnect transactions between a master device and an interconnect component. For example, a transaction intervention module coupled to an interconnect component and a master device of the interconnect component. The transaction intervention module is arranged to receive an indication of a functional state of the master device. If the master device is indicated as being in a faulty functional state the transaction intervention module is further arranged to determine whether any interconnect transactions initiated by the master device with the interconnect component are outstanding. If it is determined that at least one interconnect transaction initiated by the master device is outstanding, the transaction intervention module is arranged to finalise the at least one outstanding interconnect transaction with the interconnect component.

Abstract: A method for detecting a video signal that represents an image sequence and exhibits linewise repeated video data comprises selecting a plurality of line groups each having a first, a second and a third line, which originate from two consecutive fields in the case of a field sequence and from one field in the case of a frame sequence. The method determines for each line group a first line-distance measure for a difference between video contents of the first and second lines and a second line-distance measure for a difference between video contents of the second and third lines. The method then interprets the first and second line-distance measures with regard to the presence of a significant difference between these line-distance measures.

Abstract: A method for processing a video image sequence with a number of successive images and an image processing device for processing a video image sequence are described.

Abstract: A method for testing a motion vector is described, which has: provision of at least one item of motion information assigned to the image sequence; storing a first image section of the first image in a first buffer memory and storing a second image section of the second image in a second intermediate memory, whereby a position of the first image section in the first image and a position of the second image section in the second image have reciprocal offset, which is dependent on the at least one item of motion information; determining a first image block in the first image section and a second image block in a second image section using the motion vector; comparing the contents of the first and of the second image block.

Abstract: A method is described for selecting a motion vector for a first image block of an image of an image sequence from a number of test vectors, to which respectively a significance measurement is assigned, wherein at least one of these test vectors is a motion vector of a further image block that is arranged temporally and/or spatially adjacent to the first image block, or a vector formed by modification of this motion vector, and wherein the method covers: Determining a distance measurement for each test vector, Determining a modified distance measurement to each test vector depending on the distance measurement determined to this test vector and additionally at least on the significance measurement assigned to this test vector, Selecting one of the test vectors as motion vector depending on the modified distance measurements, Determining a new distance measurement of the test vector selected as motion vector depending on whether the selected motion vector meets at least one significance criterion, and assignin

Abstract: A method of selecting a motion vector for an image block of an image of an image sequence from a number of test vectors.

Abstract: A method for encoding first and second data words, which may represent differential data values (e.g., luminance and chrominance difference data values), onto an encoded data word includes: assigning a first code word to a first approximation value for a first data value, and assigning a second code word to second approximation value for a second data value; mapping the first and the second code words onto respective first and second data segments of the encoded data word; determining a first difference value between the first data value and the first approximation value and determining a second difference value between the second data value and the second approximation value; and at least partial mapping a first difference data word representing the first difference value and/or a second difference data word representing the second difference value onto at least one additional data segment of the encoded data word.

Abstract: The invention relates to a method for interpolating a pixel from an intermediate line of a first field of a sequence of interlaced fields.

Abstract: In a method and device for determining motion vectors that are each coordinated with individual regions of an image, the image is divided into a number of first main blocks, making use of a first block raster, and a first estimation process is performed to provide each first block with a motion vector. The image is also divided into a number of second main blocks, making use of a second block raster, whose position is displaced relative to or offset from the first block raster, for example in the horizontal and vertical directions, and a second estimation process is performed to provide each second main block with a motion vector. A number of subblocks are formed, each subblock being formed by an overlap region between one of the main blocks of the first raster and certain ones of the second main blocks of the second raster. A motion vector for each subblock is generated, this motion vector depending on the motion vectors of the main blocks and being coordinated with the particular subblock.

Abstract: A method for processing a video image sequence with a number of successive images and an image processing device for processing a video image sequence are described.

Abstract: In a method to determine a selection vector that indicates a displacement of an image area from a first position in a first image to a second position in a second image, a set of prediction vectors and a set of test vectors are provided. Using selected test vectors, an image comparison is performed to supply an image comparison result for each selected test vector. The selected test vectors and at least one prediction vector are compared to provide at least one test vector comparison result for each selected test vector. The image comparison result and the at least one test vector comparison result are linked to provide at least one quality characteristic for each selected test vector. A ranking order is determined for these quality characteristics, where at least one test vector is selected as the displacement vector based on the ranking order determined.

Abstract: The invention relates to a method for rendering an image sequence. wherein an individual image is rendered by rendering monochromatic subimages in temporal succession. A subimage sequence obtained by temporal sequencing of the subimages is generated in motion-compensated fashion.

Abstract: Method for motion-vector-aided interpolation of a pixel of an intermediate image lying between two input images includes a first pixel being selected from a first field and a second pixel being selected from a second field using a first motion vector, and a third pixel being selected from the first field and a fourth pixel being selected from the second field using a second motion vector. Next, an interval specified by video information values of the first pixel and the second pixel or an interval specified by video information values of the third pixel and the fourth pixel is determined and the video information values are mixed such that the video information value of the pixel to be interpolated lies within this interval.

Abstract: A method for testing a motion vector is described, which has: provision of at least one item of motion information assigned to the image sequence; storing a first image section of the first image in a first buffer memory and storing a second image section of the second image in a second intermediate memory, whereby a position of the first image section in the first image and a position of the second image section in the second image have reciprocal offset, which is dependent on the at least one item of motion information; determining a first image block in the first image section and a second image block in a second image section using the motion vector; comparing the contents of the first and of the second image block.