Abstract: The invention relates to a process for the distributed shielding and decoupling of an electronic device having integrated components with three-dimensional interconnection, to such a device and to a production process.

Abstract: The invention relates to a method of interconnection in three dimensions and to an electronic device obtained by this process.

Abstract: The invention relates to a method and device for interconnecting, in three dimensions, electronic components.

Abstract: The semiconductor device comprises at least one chip arranged on a support. The chip is coated with an electrically insulating and heat-stable material. This electrically insulating and heat-stable material is penetrated by electrical-connection leads connecting sites of the chip to metallized contacts, and leads are substantially perpendicular both to the said sites and to the said metallized contacts.

Abstract: A method for the interconnection of stacked packages encapsulating, for example, a semiconductor chip containing an integrated circuit, for example a memory. Packages with connection pins (21) are stacked and fixedly joined to each other by means of a coating of resin for example. The pins of the packages are cut so as to be flush with the faces (31, 32) of the stack (3). The connection (C) of the packages with one another and their connection to connection pads (35) of the stack is done on the faces of the stack. The connection pads are, if necessary, provided with connection pins (36).

Abstract: A method and device for interconnecting stacked semiconducting plates, in which each of the plates has an integrated circuit. The semiconducting plates (P) are stacked and made solid with each other. In one embodiment, their connecting contacts are connected by a wire (F) to any one of the faces of the stack except one (B), which is to be in contact with a printed circuit. Connections of the plates together and with the printed circuit is made on the faces (F.sub.V, F.sub.S, F.sub.L) of the stack.

Abstract: In a method for the interconnection of stacked packages, each of the packages encapsulating, for example, a semiconductor chip containing an integrated circuit, a memory for example, the packages provided with pins are mounted on a printed circuit board. The printed circuit boards are stacked and fixedly joined with one another by means of a coating, for example a resin coating. The stack is sliced through so as to form bars, the pins of the packages being electrically connected to the side surfaces of the bars by means of the tracks of the printed circuit boards. The connection of the packages to one another is done on the side faces of the bars. The bars are then sliced through to obtain unit blocks of stacked packages.

Abstract: A method and component resulting from interconnecting wafers in three dimensions, where the wafers include chips and the chips include pads. Steps in the method include connecting leads to the pads; stacking the wafers; embedding the stack by a selectively removable material; treating faces of the stack in order to reveal the leads; forming connections on the faces of the stack for interconnecting the leads; and removing the selectively removable material.

Abstract: A device and method for interconnection packages in a stack. Each package encapsulates, for example a semiconductor chip containing an integrated circuit, which for example may be a memory. The packages (2) which have connecting pins (21) are mounted on support grid (4) which preferably act as a heat shunt, and are stacked and linked to each other with a resin coating (5). A stack (3) is cut out so that the pins on the packages and one edge of the grids are flush with faces (31, 32) of the stack (3). Connections between the packages themselves, and between the packages and stack connecting pads, are made on the faces of the stack. The connecting pads are where necessary fitted with connecting pins.

Abstract: According to an embodiment of the invention the discrete or integrated electronic components are encapsulated, each in a package, for example a plastic one; the packages are then mounted on a printed circuit board, for example an epoxy one. The components and board as a whole are covered with a relatively thick first layer consisting of an organic compound and ensuring a levelling function, followed by a second layer such as an inorganic metal compound, the function of which is to ensure the hermetic sealing of the whole.

Abstract: Disclosed is a 3D encapsulation of semiconductor chips, each chip containing for example an integrated circuit, this encapsulation being aimed at optimising heat dissipation by conduction. Connection means are associated with each chip, making it possible to extend the pads of chips towards three sides of the chip, thus leaving the fourth side free. The chips are stacked on one another and then can be connected to heat dissipation means by their fourth side.

Abstract: An object of the invention is the production of coaxial connections for the input/output links of the component and/or of the housing which encapsulates it.More precisely, the component placed in a package (B), is conventionally connected by wires to its package; the wires are next covered by a first insulating layer (21) then by a second conducting layer (24) in such a way that this second layer is linked to the earth pads (P.sub.E1) of the package. The layers (21, 24) thus form collectively-produced coaxial structures with the connection wires (F). A similar process is used for the input/output connections (P) of the package itself.

Abstract: The invention provides a device for distributing electric potentials for supplying a component with electric power, capable of being incorporated in the case in which the component is encapsulated.This device is in the form of a plate comprising conducting planes connected to external power supply potentials. This plate either forms the cover of the case or is placed inside the case above said component. Each of the conducting planes of the device is connected, outside the case, to the power supply potential and, inside the case, at multiple points to the component so as to distribute these potentials to the appropriate inputs/outputs thereof, thus reducing the number of inputs/outputs of the case.

Abstract: A device and method are disclosed for connecting an electronic component so that it can be tested and mounted. According to the method, pads on the component are first connected to pads on a surrounding frame, by means of conducting wires. The component is tested by probes of the testing instruments to the pads of the surrounding frame. When the tests are done, the component and its frame is placed on the substrate on which it has to be mounted. The pads of the component are connected to pads on the substrate by the wires used for connection to the pads of the surrounding frame. After connection, the wires are cut between the substrate pads and the frame pads, and then the frame is removed.

Abstract: A housing more particularly intended for encapsulating a wafer scale electronic circuit, realized in hybrid technology or integrated on semi-conducting substrate. In this housing:supply voltages are brought to different points disposed over the surface of the circuitlead-in circuits are constituted by conducting planes, placed in superimposed layers in the cover or the base of the housing.

Abstract: An electronic box having a capacitor in the form of a supporting plate bearing a component and covered by a cap. Additionally, the box includes a capacitor connected onto the supporting plate in such a way as to be situated between the component and the cap.

Abstract: A casing for protecting electronic components or circuits against ionizing radiations, comprising an alternance of layers of materials having low and high atomic charge numbers, forming a multi-layer capacitor, and a base comprising an alternation of the same type.

Abstract: A device for the protection of an electronic component and/or of a circuit, integrated in the carrier of the latter, against the disturbances (voltages) generated by an external electromagnetic field. It principally comprises an electrical connection (frame) whose conductivity increases considerably under the action of the external field, between each of the outlet connections of the component which is to be protected. This electrical connection is formed by a varistance and an electrode connected to the earth of the device.

Abstract: A hermetically sealed encapsulation package for electronic components and integrated or hybrid electronic circuits has a base on which the component or circuit is mounted in the conventional manner and a cover. In one embodiment, the base includes a layer of a material which is able to retain any water molecules which might remain within the package after sealing or which may result from in-leakage from the surrounding atmosphere.

Abstract: A composite substrate, electrically insulating and with high heat conduction, for semiconductor circuits housing. It comprises principally an electrically insulating material such as alumina, in the form of a honeycombed wafer with cells, and a heat conducting material placed in said cells, such as a metal.