Abstract: A receiver includes a tunable receiving chain, configured to receive a subframe header when tuned to a first receiving bandwidth; a decoder, configured to decode an allocation information from the subframe header, the allocation information indicating an allocation of a plurality of resource blocks in the subframe; and a controller, configured to derive a second receiving bandwidth from the allocation information and to tune the receiving chain to the second receiving bandwidth.

Abstract: A receiver includes a tunable receiving chain, configured to receive a subframe header when tuned to a first receiving bandwidth; a decoder, configured to decode an allocation information from the subframe header, the allocation information indicating an allocation of a plurality of resource blocks in the subframe; and a controller, configured to derive a second receiving bandwidth from the allocation information and to tune the receiving chain to the second receiving bandwidth.

Abstract: A digital phase-locked loop has a digitally controlled oscillator with a first coarse tuning field for coarse tuning of the oscillator frequency, a second coarse tuning field for tuning of the oscillator frequency at finer intervals than the first coarse tuning field, and a fine tuning field for tuning the oscillator to an output frequency at finer intervals than the second coarse tuning field. The second coarse tuning field provides open loop tuning and is linear and connected parallel to the first coarse tuning field. The second coarse tuning field provides wide field temperature compensation and frequency error determination at start up based on an interpolated frequency value obtained prior to start up. Faster settling is provided with less complex algorithms.

Abstract: A receiver includes a tunable receiving chain, configured to receive a subframe header when tuned to a first receiving bandwidth; a decoder, configured to decode an allocation information from the subframe header, the allocation information indicating an allocation of a plurality of resource blocks in the subframe; and a controller, configured to derive a second receiving bandwidth from the allocation information and to tune the receiving chain to the second receiving bandwidth.

Abstract: A digital phase-locked loop has a digitally controlled oscillator with a first coarse tuning field for coarse tuning of the oscillator frequency, a second coarse tuning field for tuning of the oscillator frequency at finer intervals than the first coarse tuning field, and a fine tuning field for tuning the oscillator to an output frequency at finer intervals than the second coarse tuning field. The second coarse tuning field provides open loop tuning and is linear and connected parallel to the first coarse tuning field. The second coarse tuning field provides wide field temperature compensation and frequency error determination at start up based on an interpolated frequency value obtained prior to start up. Faster settling is provided with less complex algorithms.

Abstract: Examples provide a system, a phase locked loop, an apparatus, a method and a computer program for generating a clock signal, a transceiver, and a mobile terminal. A system comprises clock generator (10) configured to output provide a clock signal having a predefined average clock rate, a reference signal generator (14) configured to provide a reference signal, and a clock divider (16) configured to divide the reference signal to generate the clock signal, wherein a time difference between a clock cycles and a subsequent clock cycle of the clock signal is irregular.

Abstract: A receiver includes a tunable receiving chain, configured to receive a subframe header when tuned to a first receiving bandwidth; a decoder, configured to decode an allocation information from the subframe header, the allocation information indicating an allocation of a plurality of resource blocks in the subframe; and a controller, configured to derive a second receiving bandwidth from the allocation information and to tune the receiving chain to the second receiving bandwidth.

Abstract: A phase locked loop system includes bias voltage adjustment circuitry and a voltage regulator that outputs a smoothed core voltage to an oscillator. The bias voltage adjustment circuitry is configured to compute a scaled bias voltage based at least on a target frequency for the oscillator. The voltage regulator is configured to input i) the scaled bias voltage and ii) a selected core voltage that is selected based on the target operating frequency of the oscillator and generate the smoothed core voltage for output to the oscillator.

Abstract: Examples provide a system, a phase locked loop, an apparatus, a method and a computer program for generating a clock signal, a transceiver, and a mobile terminal. A system comprises clock generator (10) configured to output provide a clock signal having a predefined average clock rate, a reference signal generator (14) configured to provide a reference signal, and a clock divider (16) configured to divide the reference signal to generate the clock signal, wherein a time difference between a clock cycles and a subsequent clock cycle of the clock signal is irregular.

Abstract: A phase locked loop system includes bias voltage adjustment circuitry and a voltage regulator that outputs a smoothed core voltage to an oscillator. The bias voltage adjustment circuitry is configured to compute a scaled bias voltage based at least on a target frequency for the oscillator.

Abstract: Performance indicator circuitry is provided for characterizing performance of a phase locked loop (PLL) in a phase path of a polar modulator or polar transmitter that is used to generate a phase modulated RF signal. The PLL includes an oscillator, a high pass path, and a low pass path. The low pass path includes a loop filter. The performance indicator circuitry includes first input circuitry and parameter calculation circuitry. The first input circuitry is configured to input a loop filter signal from the loop filter. The parameter calculation circuitry is configured to compute a value for a performance indicator based on the loop filter signal and control or characterize an aspect of operation of the PLL based on the value.

Abstract: A phase locked loop includes a feedforward path receiving a reference signal having a reference frequency and outputting an output signal having an output frequency that is a function of the reference signal and a feedback signal. The phase locked loop further includes a feedback path having a divider circuit associated therewith that is configured to receive the output signal and generate the feedback signal having a reduced frequency based on a divide value of the divider circuit. The feedback signal is supplied to the feedforward path. The phase locked loop also includes a modulator circuit configured to receive modulation data and provide a divider control signal to the divider circuit to control the divide value thereof, and a phase tracker circuit configured to determine an amount of phase drift from an initial phase value of the output signal due to an interruption in a locked state of the phase locked loop.

Abstract: A phase locked loop system comprises a phase locked loop and an oscillator that is coarse tuned and fine tuned according to coarse tuning operations and fine tuning operations. The system operates to calibrate the coarse tuning of the oscillator based on one or more characteristics related to the oscillator and determined by a characterization component, an interpolation function and one or more final measurements. An adjustment component is configured to adjust the coarse tuning value based on at least one final frequency measurement to generate a final coarse tuning value and set the coarse tuning of the oscillator based on the final coarse tuning value.

Abstract: A phase locked loop system comprises a phase locked loop and an oscillator that is coarse tuned and fine tuned according to coarse tuning operations and fine tuning operations. The system operates to calibrate the coarse tuning of the oscillator based on one or more characteristics related to the oscillator and determined by a characterization component, an interpolation function and one or more final measurements.

Abstract: A phase locked loop includes a feedforward path receiving a reference signal having a reference frequency and outputting an output signal having an output frequency that is a function of the reference signal and a feedback signal. The phase locked loop further includes a feedback path having a divider circuit associated therewith that is configured to receive the output signal and generate the feedback signal having a reduced frequency based on a divide value of the divider circuit. The feedback signal is supplied to the feedforward path. The phase locked loop also includes a modulator circuit configured to receive modulation data and provide a divider control signal to the divider circuit to control the divide value thereof, and a phase tracker circuit configured to determine an amount of phase drift from an initial phase value of the output signal due to an interruption in a locked state of the phase locked loop.

Abstract: One embodiment of the present invention relates to a modulation system having a phase locked loop and an adaptive control. The phased lock loop is configured to receive an input signal and an adaptive signal. The input signal is an unmodulated signal, such as a phase component or phase signal. The phase locked loop is also configured to provide an error signal and an output signal. The error signal indicates one or more modulation errors. The output signal is a modulated version of the input signal that has been corrected using the adaptive signal to mitigate the one or more modulation errors.

Abstract: One embodiment of the present invention relates to a modulation system having a phase locked loop and an adaptive control. The phased lock loop is configured to receive an input signal and an adaptive signal. The input signal is an unmodulated signal, such as a phase component or phase signal. The phase locked loop is also configured to provide an error signal and an output signal. The error signal indicates one or more modulation errors. The output signal is a modulated version of the input signal that has been corrected using the adaptive signal to mitigate the one or more modulation errors.

Abstract: A circuit includes an oscillator, a variable phase adjuster and a feedback loop. The oscillator is configured to provide an RF signal, wherein the oscillator is configured to operate in a free-running mode of operation. The variable phase adjuster is configured to provide a phase adjusted signal, a phase of which is shifted with respect to a phase of an output signal of the oscillator, or with respect to a phase of a signal derived from the output signal of the oscillator. The feedback loop is configured to provide a control value for controlling the variable phase adjuster based on the phase adjusted signal and a reference oscillator signal to counteract a phase error of the phase adjusted signal.

Abstract: The present disclosure relates to a frequency synthesizer. The frequency synthesizer includes a phase comparator having first and second input nodes. The first input node receives a reference signal having a reference frequency. A channel control block has an input that receives a channel word and an output coupled to the second input node of the phase comparator. A local oscillator (LO) output node provides an LO signal having an LO frequency based on the reference frequency and the channel word. A feedback back couples the LO output node to the second input node of the phase comparator through the channel control block. A non-linear error correction element is operably coupled on a coupling path extending between the phase comparator and the DCO.

Abstract: A phase locked loop has a controlled oscillator for outputting an oscillator signal depending on a control signal. A comparator generates a comparison result from a comparison between a reference frequency signal and a feedback signal derived from the oscillator signal. The phase locked loop also has a filter block for filtering the comparison result and for deriving the control signal from the comparison result, where the filter block has a loop filter and a rejection filter for the frequency-selective attenuation of at least one first interference frequency in the comparison result.