Patents by Inventor Christian Witt

Christian Witt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11145349
    Abstract: Disclosed is a memory cell including parallel-connected first access transistors and a first variable resistor in series between a bitline and a source line and parallel-connected second access transistors and a second variable resistor in series between the bitline and the source line. A write wordline controls one pair of first and second access transistors so that, during an initialization mode, the resistors are concurrently subjected to the same write bias conditions for one-time programming to switch from an unprogrammed state (where the resistors have the same first resistance state) to a programmed state (where one resistor has switched to a second resistance state and a bit is stored). Discrete first and second read wordlines control another pair of first and second access transistors to enable discrete read processes associated with the first and second variable resistors. Also disclosed are an associated circuit (e.g., a PUF) and a method.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: October 12, 2021
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Bartlomiej J. Pawlak, Christian A. Witt
  • Patent number: 10916139
    Abstract: A system and method to capture and aggregate occupant and incident information from within a vehicle following an accident, and to transmit such aggregated incident and patient data, in an automated and event triggered fashion, to an emergency responder. The data transmitted to the emergency responder can trigger creating a new patient record for the occupant of the vehicle.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: February 9, 2021
    Inventors: Jonathon S. Feit, Christian Witt
  • Patent number: 10886215
    Abstract: Example embodiments relate to interconnect structures and related methods. One embodiment includes an interconnect structure. The interconnect structure includes a first interconnection level including a first dielectric layer and a first set of conductive paths. The interconnect structure also includes a second interconnection level arranged above the first interconnection level and including a second dielectric layer and a second set of conductive paths. Further, the interconnect structure includes a third interconnection level arranged above the second interconnection level and including a third dielectric layer and a third set of conductive paths. In addition, the interconnect structure includes a fourth interconnection level arranged above the third interconnection level and including a fourth dielectric layer and a fourth set of conductive paths. Still further, the interconnect structure includes a first multi-level via structure and a second multi-level via structure.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: January 5, 2021
    Assignee: IMEC VZW
    Inventors: Houman Zahedmanesh, Victoria L. Calero Diaz Del Castillo, Christian Witt
  • Publication number: 20200105667
    Abstract: Example embodiments relate to interconnect structures and related methods. One embodiment includes an interconnect structure. The interconnect structure includes a first interconnection level including a first dielectric layer and a first set of conductive paths. The interconnect structure also includes a second interconnection level arranged above the first interconnection level and including a second dielectric layer and a second set of conductive paths. Further, the interconnect structure includes a third interconnection level arranged above the second interconnection level and including a third dielectric layer and a third set of conductive paths. In addition, the interconnect structure includes a fourth interconnection level arranged above the third interconnection level and including a fourth dielectric layer and a fourth set of conductive paths. Still further, the interconnect structure includes a first multi-level via structure and a second multi-level via structure.
    Type: Application
    Filed: July 24, 2019
    Publication date: April 2, 2020
    Inventors: Houman Zahedmanesh, Victoria L. Calero Diaz Del Castillo, Christian Witt
  • Patent number: 10580696
    Abstract: Structures for interconnects and methods of forming interconnects. An interconnect opening in a dielectric layer includes a first portion and a second portion arranged over the first portion. A first conductor layer composed of a first metal is arranged inside the first portion of the interconnect opening. A second conductor layer composed of a second metal is arranged inside the second portion of the interconnect opening. The first metal is ruthenium.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: March 3, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sean Xuan Lin, Christian Witt, Mark V. Raymond, Nicholas V. LiCausi, Errol Todd Ryan
  • Publication number: 20200066585
    Abstract: Structures for interconnects and methods of forming interconnects. An interconnect opening in a dielectric layer includes a first portion and a second portion arranged over the first portion. A first conductor layer composed of a first metal is arranged inside the first portion of the interconnect opening. A second conductor layer composed of a second metal is arranged inside the second portion of the interconnect opening. The first metal is ruthenium.
    Type: Application
    Filed: August 21, 2018
    Publication date: February 27, 2020
    Inventors: Sean Xuan Lin, Christian Witt, Mark V. Raymond, Nicholas V. LiCausi, Errol Todd Ryan
  • Patent number: 10224284
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a soluble self-aligned barrier first for interconnect structure and methods of manufacture. The structure includes: a self-aligning barrier layer lining a trench of an interconnect structure; and an alloy interconnect material over the self-aligned barrier layer. The alloy interconnect material is an alloy composed of metal interconnect material and pre-anneal material that also forms the self-aligning barrier layer.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: March 5, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Christian A. Witt
  • Patent number: 10109524
    Abstract: The disclosure relates to integrated circuit (IC) fabrication techniques. Methods according to the disclosure can include: forming a reaction layer on the upper surface of a conductor, the upper surface of a refractory metal liner, and the upper surface of an insulator layer; annealing the reaction layer such that a portion of the reaction layer reacts with the conductor to form a semiconductor-metal alloy region; removing a portion of the reaction layer to expose the refractory metal liner; removing a portion of the refractory metal liner to approximately a depth of the semiconductor-metal alloy region; and removing the semiconductor-metal alloy region to expose a portion of the conductor such that a remainder of the conductor and a remainder of the refractory metal liner are recessed relative to an upper surface of the insulator layer.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: October 23, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Christian A. Witt
  • Publication number: 20180211873
    Abstract: The disclosure relates to integrated circuit (IC) fabrication techniques. Methods according to the disclosure can include: forming a reaction layer on the upper surface of a conductor, the upper surface of a refractory metal liner, and the upper surface of an insulator layer; annealing the reaction layer such that a portion of the reaction layer reacts with the conductor to form a semiconductor-metal alloy region; removing a portion of the reaction layer to expose the refractory metal liner; removing a portion of the refractory metal liner to approximately a depth of the semiconductor-metal alloy region; and removing the semiconductor-metal alloy region to expose a portion of the conductor such that a remainder of the conductor and a remainder of the refractory metal liner are recessed relative to an upper surface of the insulator layer.
    Type: Application
    Filed: January 24, 2017
    Publication date: July 26, 2018
    Inventor: Christian A. Witt
  • Publication number: 20170270252
    Abstract: A system and method to capture and aggregate occupant and incident information from within a vehicle following an accident, and to transmit such aggregated incident and patient data, in an automated and event triggered fashion, to an emergency responder. The data transmitted to the emergency responder can trigger creating a new patient record for the occupant of the vehicle.
    Type: Application
    Filed: March 17, 2017
    Publication date: September 21, 2017
    Inventors: Jonathon S. Feit, Christian Witt
  • Patent number: 9768058
    Abstract: One illustrative method disclosed herein includes, among other things, forming a plurality of trenches in a layer of insulating material, performing at least one damage-causing process operation to selectively damage portions of the insulating material adjacent the trenches, forming a conductive line in each of the trenches, after forming the conductive lines, performing a selective etching process to selectively remove at least portions of the damaged portions of the insulating material and thereby define an air gap positioned laterally adjacent each of the conductive lines, and forming a capping layer of material above the conductive lines, the air gap and the undamaged portion of the layer of insulating material.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: September 19, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Zhiguo Sun, Qiang Fang, Christian Witt
  • Publication number: 20170047242
    Abstract: One illustrative method disclosed herein includes, among other things, forming a plurality of trenches in a layer of insulating material, performing at least one damage-causing process operation to selectively damage portions of the insulating material adjacent the trenches, forming a conductive line in each of the trenches, after forming the conductive lines, performing a selective etching process to selectively remove at least portions of the damaged portions of the insulating material and thereby define an air gap positioned laterally adjacent each of the conductive lines, and forming a capping layer of material above the conductive lines, the air gap and the undamaged portion of the layer of insulating material.
    Type: Application
    Filed: August 10, 2015
    Publication date: February 16, 2017
    Inventors: Zhiguo Sun, Qiang Fang, Christian Witt
  • Patent number: 9440531
    Abstract: A power-train is provided for a driven, steerable axle of a motor vehicle. To reduce the size of the turning radius of the vehicle, the power train includes a left drive shaft that is fixedly connected in terms of drive to a left steerable wheel; a right drive shaft that is fixedly connected in terms of drive to a right steerable wheel; and a drive unit configured between the drive shafts for driving the drive shaft; the drive shafts being configured as articulated shafts, each having a wheel-proximal articulated joint and a wheel-distal articulated joint; and said articulated joints each having at least one axis of rotation with the same orientation for all articulated joints. The drive unit is designed for transmitting an electromotively generated torque to the drive shafts, and having a body suspension that allows the drive unit to rotate relative to the body about a swivel axis that extends in parallel to the axes of rotation having the same orientation.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: September 13, 2016
    Assignee: Schaeffler Technologies AG & Co. KG
    Inventors: Raphael Fischer, Thorsten Schubert, Thomas Mehlis, Christian Witt
  • Publication number: 20160104672
    Abstract: A method of electrically connecting first and second conductive features includes forming a first metallization layer including the first conductive feature. A ballistic conductor line is formed above the first metallization layer. The ballistic conductor line contacts the first conductive feature proximate a first end of the ballistic conductor line. The second conductive feature is contacted proximate a second end of the ballistic conductor line.
    Type: Application
    Filed: October 10, 2014
    Publication date: April 14, 2016
    Inventors: Roderick A. Augur, Christian Witt
  • Publication number: 20160104670
    Abstract: A method includes forming a ballistic conductor line above a first metallization layer. A dielectric layer is formed above the ballistic conductor line. A first via is embedded in the dielectric layer contacting a first portion of the ballistic conductor line. A second via is embedded in the dielectric layer contacting a second portion of the ballistic conductor line to define a signal path between the first and second vias through the ballistic conductor line.
    Type: Application
    Filed: October 10, 2014
    Publication date: April 14, 2016
    Inventors: Roderick A. Augur, Christian Witt
  • Patent number: 9236299
    Abstract: One method includes forming a barrier layer in a trench/opening in an insulating material, forming a first region of a copper material above the barrier layer, forming a metal layer in the trench/opening on the first region of copper material, forming a second region of copper material on the metal layer, performing at least one CMP process to remove any materials positioned above a planarized upper surface of the layer of insulating material outside of the trench/opening so as to thereby define a structure comprised of the metal layer positioned between the first and second regions of copper material, forming a dielectric cap layer above the layer of insulating material and above the structure, and performing a metal diffusion anneal process to form a metal cap layer adjacent at least the upper surface of a conductive copper structure.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: January 12, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Xunyuan Zhang, Hoon Kim, Christian Witt, Larry Zhao
  • Publication number: 20150255339
    Abstract: One method includes forming a barrier layer in a trench/opening in an insulating material, forming a first region of a copper material above the barrier layer, forming a metal layer in the trench/opening on the first region of copper material, forming a second region of copper material on the metal layer, performing at least one CMP process to remove any materials positioned above a planarized upper surface of the layer of insulating material outside of the trench/opening so as to thereby define a structure comprised of the metal layer positioned between the first and second regions of copper material, forming a dielectric cap layer above the layer of insulating material and above the structure, and performing a metal diffusion anneal process to form a metal cap layer adjacent at least the upper surface of a conductive copper structure.
    Type: Application
    Filed: March 7, 2014
    Publication date: September 10, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Xunyuan Zhang, Hoon Kim, Christian Witt, Larry Zhao
  • Patent number: 9054052
    Abstract: A process is provided for methods of reducing damage to an ultra-low k layer during fabrication. In one aspect, a method includes: providing a cured ultra-low k film containing pores filled with a pore-stuffing material; and modifying an exposed surface of the ultra-low k film to provide a modified layer in the ultra-low k film. In another aspect, a semiconductor device comprising a modified layer on a surface of an ultra-low k film is provided.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: June 9, 2015
    Assignee: GLOBAL FOUNDRIES INC.
    Inventors: Nicholas Vincent Licausi, Errol Todd Ryan, Ming He, Moosung M. Chae, Kunaljeet Tanwar, Larry Zhao, Christian Witt, Ailian Zhao, Sean X. Lin, Xunyuan Zhang
  • Patent number: 8932934
    Abstract: A process is provided for methods of reducing contamination of the self-forming barrier of an ultra-low k layer during semiconductor fabrication. In one aspect, a method includes: providing a cured ultra-low k film which contains at least one trench, and the pores of the film are filled with a pore-stuffing material; removing exposed pore-stuffing material at the surface of the trench to form exposed pores; and forming a self-forming barrier layer on the surface of the trench.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: January 13, 2015
    Assignee: Global Foundries Inc.
    Inventors: Moosung M. Chae, Errol Todd Ryan, Nicholas Vincent Licausi, Christian Witt, Ailian Zhao, Ming He, Sean X. Lin, Xunyuan Zhang, Kunaljeet Tanwar
  • Publication number: 20140374185
    Abstract: A power-train is provided for a driven, steerable axle of a motor vehicle. To reduce the size of the turning radius of the vehicle, the power train includes a left drive shaft that is fixedly connected in terms of drive to a left steerable wheel; a right drive shaft that is fixedly connected in terms of drive to a right steerable wheel; and a drive unit configured between the drive shafts for driving the drive shaft; the drive shafts being configured as articulated shafts, each having a wheel-proximal articulated joint and a wheel-distal articulated joint; and said articulated joints each having at least one axis of rotation with the same orientation for all articulated joints. The drive unit is designed for transmitting an electromotively generated torque to the drive shafts, and having a body suspension that allows the drive unit to rotate relative to the body about a swivel axis that extends in parallel to the axes of rotation having the same orientation.
    Type: Application
    Filed: January 17, 2013
    Publication date: December 25, 2014
    Inventors: Raphael Fischer, Thorsten Schubert, Thomas Mehlis, Christian Witt