Abstract: Methods of forming a memory cell containing two split sub-lithographic charge storage nodes on a semiconductor substrate are provided. The methods can involve forming two split sub-lithographic charge storage nodes by using spacer formation techniques. By removing exposed portions of a first poly layer while leaving portions of the first poly layer protected by the spacers, the method can provide two split sub-lithographic first poly gates. Further, by removing exposed portions of a charge storage layer while leaving portions of the charge storage layer protected by the two split sub-lithographic first poly gates, the method can provide two split, narrow portions of the charge storage layer, which subsequently form two split sub-lithographic charge storage nodes.

Abstract: A method for fabrication and a structure of a self-aligned (crosspoint) memory device comprises lines (wires) in a first direction and in a second direction. The wires in the first direction are formed using a hard mask material that is resistant to the pre-selected etch processes used for creation of the lines in both the first and the second direction. Consequently, the hard mask material for the lines in the first direction form part of the memory stack.

Abstract: Methods of forming a memory cell containing two split sub-lithographic charge storage nodes on a semiconductor substrate are provided. The methods can involve forming two split sub-lithographic charge storage nodes by using spacer formation techniques. By removing exposed portions of a first poly layer while leaving portions of the first poly layer protected by the spacers, the method can provide two split sub-lithographic first poly gates. Further, by removing exposed portions of a charge storage layer while leaving portions of the charge storage layer protected by the two split sub-lithographic first poly gates, the method can provide two split, narrow portions of the charge storage layer, which subsequently form two split sub-lithographic charge storage nodes.

Abstract: A method for fabrication and a structure of a self-aligned (crosspoint) memory device comprises lines (wires) in a first direction and in a second direction. The wires in the first direction are formed using a hard mask material that is resistant to the pre-selected etch processes used for creation of the lines in both the first and the second direction. Consequently, the hard mask material for the lines in the first direction form part of the memory stack.

Abstract: A method and structure for a memory cell comprising a phase change material; a heating element in thermal contact with the phase change material, wherein the heating element is adapted to induce a phase change in the phase change material; and electrical lines configured to pass current through the heating element, wherein the phase change material and the heating element are arranged in a configuration other than being electrically connected in series. The memory cell further comprises a sensing element in thermal contact with the phase change material, wherein the sensing element is adapted to detect a change in at least one physical property of the phase change material, wherein the sensing element is adapted to detect a change in a thermal conductivity of the phase change material.

Abstract: A fiducial beam monitor includes a patterned diode layer on a semiconducting substrate. An electrical field between the diode (or diodes) on the diode layer and the semiconducting substrate modulates the size of the depletion layer formed by the diode or diode. A high energy beam incident upon a diode on the diode layer produces a greater current than a high energy beam incident upon a non-diodic region of the same layer. In use, the beam monitor is typically fixed to the backside of a workpiece such as a semitransparent membrane being patterned by a focused high energy beam that is translated with respect to workpiece and attached monitor. The changes in current during translation are then correlated with the position of the beam with respect to the pattern on the diode layer.

Abstract: Improvement in resolution in terms of minimum feature sizes and proximity fects in an electronic mask is attained by making the mask using a high voltage electron beam which deflects or blocks backscattered electrons. The novel mask structure comprises a transparent support, an absorber layer disposed on said support, a dielectric layer disposed on said absorber layer, and a resist layer disposed on said dielectric layer. It is the dielectric layer which is credited for improving resolution in said mask which can be used a multiple number of times in printing a pattern for various applications, including electronic devices and integrated circuits.

Abstract: A method and apparatus for bonding a layer of coating material onto a subate with minimal bulk heating of the substrate. A pulsed electron beam generator is used to produce high energy electrons at the beginning of the pulse and a larger number of lower energy electrons at the end of the pulse. A thin sacrificial or ablative layer of an easily-vaporized material such as tin is placed on top the coating. The high energy electrons penetrate through the ablative and coating layers. The ablative layer is heated to a molten state, causing it to vaporize. The ablation process generates a force on the coating layer which drives it into the substrate.

Abstract: Sidewalls in a pattern of a refractory metal on a substrate are passivated during plasma etching by introducing water vapor into the etching chamber. This process obtains nearly vertical sidewalls. In one exemplified embodiment, a pattern of tungsten on a chromium etch step layer was reactive ion etched. In that embodiment, the reactive ion etching was intermittently paused. After each pause, the workpiece was warmed from below about 20.degree. C. to about room temperature. Then, water vapor was introduced into the etching chamber housing the workpiece. After the water vapor was introduced, the workpiece was cooled to below about 20.degree. C. and reactive ion etching was resumed. Alternatively, water vapor can be introduced into the etching chamber continuously during plasma etching.

Abstract: An apparatus and method lithographically patterns an imaging layer using a predetermined pattern. The apparatus includes a cantilever having a tip attached thereto, which tip includes a conductive or semiconductive material. The apparatus also includes a scanning probe controller connected to the cantilever, which maintains the tip in contact with the imaging layer to be patterned. Substantially while the scanning probe controller maintains the tip in contact with the imaging layer, a voltage and/or current generator coupled to the tip selectively generates a voltage and/or current between the tip and the imaging layer to affect a physical change in the imaging layer based on the predetermined pattern. The physical change in the imaging layer can be exploited to fabricate integrated circuits, lithographic masks or micromechanical devices, for example. The scanning probe controller can also measure the topographical change in the imaging layer caused by the physical change using the same cantilever and tip.

Abstract: Improvement of resolution in terms of reducing minimum feature sizes and ximity effects on bulk substrates in high voltage electron beam lithography as applied to manufacture of electronic circuits from coated semiconductors involves the use of a dielectric layer interposed between an electrically semiconducting substrate and a resist layer. The dielectric layer functions to reduce the resist exposure resulting from the backscattered electrons coming from the substrate into the resist layer.

Abstract: A neural net, and method of using the net, to solve ill-posed problems, such as deconvolution in the presence of noise. The net is of the Tank-Hopfield kind, in which input to the signal net is a cross entropy regularizer.

Abstract: A process for producing metal plated paths on a solid substrate of the kind which has polar functional groups at its surface, utilizing a self-assembling film that is chemically absorbed on the substrate's surface. The solid substrate may, for example, be an insulator of the kind used for substrates in printed circuitry or may, as another example, be a semiconductor of the kind used in semiconductor microcircuitry. The chemical reactivity in regions of the ultra-thin film is altered to produce a desired pattern in the film. A catalytic precursor which adheres only to those regions of the film having enough reactivity to bind the catalyst is applied to the film's surface. The catalyst coated structure is then immersed in an electroless plating bath where metal plates onto the regions activated by the catalyst.

Abstract: A process for producing metal plated paths on a solid substrate of the kind which has polar functional groups at its surface utilizes a self-assembling monomolecular film that is chemically adsorbed on the substrate's surface. The solid substrate may, for example, be an insulator of the kind used for substrates in printed circuitry or may, as another example, be a semiconductor of the kind used in semiconductor microcircuitry. The chemical reactivity in regions of the ultra-thin film is altered to produce a desired pattern in the film. A catalytic precursor which adheres only to those regions of the film having enough reactivity to bind the catalyst is applied to the film's surface. The catalyst coated structure is then immersed in an electrolers plating bath where metal plates onto the regions activated by the catalyst.

Abstract: Disclosed are two modifications of the Tank-Hopfield circuit, each of which enables the deconvolution of a signal in the presence of noise. In each embodiment, the Tank-Hopfield circuit is modified so that the equation for total circuit energy reduces to one term representing convolution and another information theoretic (or Shannon) entropy. Thus, in finding its global minimum energy state, each modified circuit inherently identifies an optimal estimate of a deconvoluted input signal without noise.

Abstract: A method for predicting the proclivity of various materials to emit electrons, and thus their suitability for cathode fabrication. The method includes steps to determine the surface work function lowering by analyzing and comparing the Auger electron-energy spectra of a plurality of sample materials.