Abstract: A CMOS image sensor includes a plurality of pixels arranged column and rows in an array; a column circuit for storing reset values and a value after integration; a correlated double sampler which derives an image signal from the reset and the value after integration; and an anti-eclipse circuit physically separately from the column circuit and electrically connected to one or shared between multiple columns of pixels for restoring corrupted column voltage on a column of pixels.

Abstract: A CMOS image sensor includes a plurality of pixels arranged column and rows in an array; a column circuit for storing reset values and a value after integration; a correlated double sampler which derives an image signal from the reset and the value after integration; and an anti-eclipse circuit physically separately from the column circuit and electrically connected to one or shared between multiple columns of pixels for restoring corrupted column voltage on a column of pixels.

Abstract: An oversaturation protection circuit is provided within a CMOS image sensor. A detector is arranged to monitor an output column line that is associated with a pixel to determine whether the pixel is oversaturated after being reset. If the pixel is oversaturated after being reset, the level of the pixel is determined by measuring the difference between a first reference voltage and the integrated voltage of the pixel. If the pixel is not oversaturated after being reset, the level of the pixel is determined by measuring the difference between the voltage of the column line shortly after reset and the integrated voltage of the pixel. A detector may be arranged to provide the result of the comparison of the associated pixel to be used with other pixels within the pixel column that are adjacent to the associated pixel.

Abstract: An array of active pixel sensor cells is operated to substantially reduce the gate induced drain leakage (GIDL) current component of the dark current. In addition, the array is tested to determine the number of cells in the array that are bad, and discards the array of active pixel sensor cells when the number of bad cells exceeds a predefined limit.

Abstract: A charge-pump circuit generates a constant voltage higher than the available power supply. A feedback path maintains the voltage at a constant level in spite of power supply, temperature and process variations. This charge pump circuit includes a switched capacitor interface arranged to generate a target voltage that is used to activate and deactivate a bypass capacitor interface to maintain the constant voltage. The bypass capacitor interface is configured to complete the feedback path. The feedback helps to ensure that node n1, that is coupled to the output of the charge pump, stays at a constant potential, irrespective of the power supply voltage.

Abstract: An integrated circuit having at least one segmented array of switches, wherein the root node of each segmented array of switches is a node whose potential varies with time during operation. Each segmented switch array includes switches connected between nodes having a tree structure. The nodes include the root node and additional nodes of at least two different degrees relative to the root node. By providing a segmented array (rather than a non-segmented array) of switches at a node, the total load capacitance (including parasitic capacitance) at the node is reduced in accordance with the invention. In preferred embodiments, the invention is an analog integrated circuit having a first node at which the potential varies rapidly, and a segmented array of switches whose root node is the first node. Another aspect of the invention is a method for designing an integrated circuit to have reduced load capacitance (e.g.

Abstract: An active pixel sensor cell array including a XDR reset signal generation circuit configured to generate XDR reset signals having user-selected levels, and an XDR reset signal generation circuit for use with such an array. The XDR reset signal generation circuit includes a digital-to-analog converter (DAC) coupled to receive control bits which determine the level and time of assertion of each XDR reset signal, and a level shifting circuit coupled to the output of the DAC. In response to the control bits (typically a sequence of multi-bit words), the circuit asserts a time-varying XDR reset potential. The XDR reset potential's amplitude as function of time (during each integration period) determines the breakpoints of each cell's response curve.