Abstract: A resistive element having two vertical resistive portions placed in two holes formed in the upper portion of a substrate and a horizontal resistive portion placed in a buried cavity connecting the bottoms of the holes.

Abstract: A resistive element having two vertical resistive portions placed in two holes formed in the upper portion of a substrate and a horizontal resistive portion placed in a buried cavity connecting the bottoms of the holes.

Abstract: A resistive element having two vertical resistive portions placed in two holes formed in the upper portion of a substrate and a horizontal resistive portion placed in a buried cavity connecting the bottoms of the holes.

Abstract: A method for forming, in a semiconductor substrate, wells and/or trenches having different destinations, including the steps of at least partly simultaneously etching cavities according to the pattern of the trenches and/or wells; closing the openings of the cavities with at least one first non-conformal thick layer, and selectively opening the first thick layer according to the subsequent processings.

Abstract: A resistive element having two vertical resistive portions placed in two holes formed in the upper portion of a substrate and a horizontal resistive portion placed in a buried cavity connecting the bottoms of the holes.

Abstract: A method for forming, in a semiconductor substrate, wells and/or trenches having different destinations, including the steps of at least partly simultaneously etching cavities according to the pattern of the trenches and/or wells; closing the openings of the cavities with at least one first non-conformal thick layer, and selectively opening the first thick layer according to the subsequent processings.

Abstract: A method of forming an isolating wall in a semiconductor substrate of a first conductivity type, including the steps of boring in the substrate separate recesses according to the desired isolating wall contour; filling the recesses with a material containing a dopant of the second conductivity type; and performing an anneal step so that regions of the second conductivity type diffused from neighboring recesses join. A first series of recesses is formed from the upper surface and a second series of recesses is formed from the lower surface. The recesses have a substantially rectangular section, the large dimension of which is perpendicular to the alignment of the recesses and a depth smaller than or equal to the half-thickness of the substrate.

Abstract: A method for manufacturing, on a silicon substrate, a capacitor of high capacitance, including the following successive steps, coating the substrate with a first insulating layer, successively forming and etching on the substrate, a first electrode, a dielectric made of a ferroelectric material with a high dielectric constant and, a second electrode, coating the structure with a second insulating layer for encapsulating the capacitor structure, forming contact openings towards semiconductor areas and towards the first electrode of the capacitor, depositing and etching a first conductive layer, depositing a third protective insulating layer, depositing a second conductive layer establishing, in particular, a contact with the upper electrode of the component, and depositing a final passivation layer.

Abstract: A method of forming an insulated well in an upper portion of a silicon substrate, including the steps of providing a structure of silicon-on-insulator type including a silicon substrate, an insulating layer, and a thin single-crystal silicon layer; removing the insulating layer and the thin silicon layer outside locations where the insulated well is desired to be formed; growing an epitaxial layer; performing a planarization; and making a vertical insulating wall above the periphery of the maintained portion of the thin insulating layer.

Abstract: A monolithic protection component is formed in a P-type low-doped semiconductor substrate. The protection diode comprises, in an upper surface of the substrate, a first and a second N-type well with a mean doping level; at the surface of the first well, a first highly doped P region; at the surface of the second well, a second very highly doped N region; a third very highly doped N region laterally contacting the first well; a fourth highly-doped P region beneath a portion of the lower surface of the third region; a first metallization contacting the surface of the first and second regions which constitute the first diode terminal; and a second metallization coupled to a P-type area extending up to the fourth region and second well, which forms the second terminal of the diode. The protection component provides a unidirectional protection diode. Two of the protection components may be combined in a single structure to provide a bidirectional protection diode.

Abstract: A monolithic protection component is formed in a P-type low-doped semiconductor substrate. The protection diode comprises, in an upper surface of the substrate, a first and a second N-type well with a mean doping level; at the surface of the first well, a first highly doped P region; at the surface of the second well, a second very highly doped N region; a third very highly doped N region laterally contacting the first well; a fourth highly-doped P region beneath a portion of the lower surface of the third region; a first metallization contacting the surface of the first and second regions which constitute the first diode terminal; and a second metallization coupled to a P-type area extending up to the fourth region and second well, which forms the second terminal of the diode. The protection component provides a unidirectional protection diode. Two of the protection components may be combined in a single structure to provide a bidirectional protection diode.

Abstract: A monolithic structure comprises two sets of bidirectional diodes having distinct characteristics constituted from a substrate (1) of a first (N.sup.-) conductivity type. First regions (10, 11, 12) of the second conductivity type constitute the first set of diodes between a first metallization (30) coating one of the first regions and second metallizations (31, 32) coating the other first regions. In a well (15) of the second conductivity type, second regions (20, 21, 22) of the first conductivity type constitute the second set of diodes between a third metallization (40) coating one of the second regions and fourth metallizations (41, 42) coating the other second regions.

Abstract: A metallization layer forming a bonding pad is formed on a diffused region of a semiconductor substrate for making electrical connection to the diffused region. A polysilicon layer of the same conductivity type as the diffused region is formed on the diffused region, overlapping onto sidewalls and peripheral portions of a silicon oxide mask. A two-layer metallization layer comprising a first nickel layer and an overlying gold layer covers the polysilicon layer. The semiconductor device is formed by diffusing an impurity into the upper surface of a semiconductor substrate using a silicon oxide mask. A doped polysilicon layer is formed on the diffused region, overlapping onto sidewall portions and extending up onto the silicon oxide mask layer. The substrate is immersed in a metal-plating electroless bath to form layers of nickel and gold on conductive portions of the substrate including on the polysilicon and on a face of the substrate opposite the polysilicon layer.

Abstract: The instant invention relates to protection semiconductive components, thrystors or triacs. Those components do not usually comprise gate electrodes and are triggered by an overvoltage between the main electrodes. When one wishes to obtain however a gate triggering, the invention provides for a structure with a narrowed region of the gate (part D) and an overdoped central region (22) below a portion of the emitter (18). With this structure, one avoids to have a too high gate current to trigger the thyristor and a too low hold current once it is triggered.