Abstract: An integrated circuit (IC) includes a transistor, and a first layer including electrically conductive material. In an example, the first layer is conductively coupled to the transistor. The IC further includes a second layer including electrically conductive material above the first layer. The IC further includes one or more intervening layers between the first and second layers. In an example, the one or more intervening layers include at least a third layer, wherein the third layer includes (i) a first metal, (ii) oxygen, and (iii) one or both of a second metal or an oxide thereof within the third layer. In an example, the first layer, the second layer, and the one or more intervening layers form a metal-insulator-metal (MIM) capacitor. In an example, the MIM capacitor and the transistor, in combination, form a memory cell of a dynamic random access memory (DRAM) array.

Abstract: Self-aligned gate endcap (SAGE) architectures with improved caps, and methods of fabricating self-aligned gate endcap (SAGE) architectures with improved caps, are described. In an example, an integrated circuit structure includes a first gate structure over a first semiconductor fin. A second gate structure is over a second semiconductor fin. A gate endcap isolation structure is between the first gate structure and the second gate structure. The gate endcap isolation structure has a higher-k dielectric cap layer on a lower-k dielectric wall. The higher-k dielectric cap layer includes hafnium and oxygen and has 70% or greater monoclinic crystallinity.