Patents by Inventor Christine S Hau-Riege

Christine S Hau-Riege has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8482125
    Abstract: Electromigration in microbump connections causes voids in the microbumps, which reduces the lifetime of an integrated circuit containing the microbump. Electromigration lifetime may be increased in microbumps by forming a copper shell around the solder. The copper shell of one microbump contacts the copper shell of a second microbump to enclose the solder of the microbump connection. The copper shell allows higher current densities through the microbump. Thus, smaller microbumps may be manufactured on a smaller pitch without suffering failure from electromigration. Additionally, the copper shell reduces shorting or bridging between microbump connections on a substrate.
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: July 9, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Arvind Chandrasekaran, Shiqun Gu, Christine S. Hau-Riege
  • Patent number: 7135775
    Abstract: A method, apparatus, system, and machine-readable medium for an interconnect structure in a semiconductor device and its method of formation is disclosed. Embodiments comprise a carbon-doped and silicon-doped interconnect having a concentration of silicon to avoid to forming a copper silicide layer between an interconnect and a passivation layer. Some embodiments provide unexpected results in electromigration reliability in regards to activation energy and/or mean time to failure.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: November 14, 2006
    Assignee: Intel Corporation
    Inventors: Stephen T. Chambers, Valery M. Dubin, Andrew W. Ott, Christine S. Hau-Riege
  • Patent number: 6897476
    Abstract: According to one exemplary embodiment, a test structure for determining electromigration and interlayer dielectric failure comprises a first metal line situated in a metal layer of the test structure. The test structure further comprises a second metal line situated adjacent and substantially parallel to the first metal line, where the second metal line is separated from the first metal line by a first distance, and where the first distance is substantially equal to minimum design rule separation distance. The test structure further comprises an interlayer dielectric layer situated between the first metal line and the second metal line. According to this exemplary embodiment, electromigration failure is determined when a first resistance of the first metal line or a second resistance of the second metal line is greater than a predetermined resistance, and interlayer dielectric failure is determined when a first current is detected between the first and second metal lines.
    Type: Grant
    Filed: August 7, 2003
    Date of Patent: May 24, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Hyeon-Seag Kim, Seung-Hyun Rhee, Christine S Hau-Riege, Amit P Marathe
  • Publication number: 20030137050
    Abstract: A method, apparatus, system, and machine-readable medium for an interconnect structure in a semiconductor device and its method of formation is disclosed. Embodiments comprise a carbon-doped and silicon-doped interconnect having a concentration of silicon to avoid to forming a copper silicide layer between an interconnect and a passivation layer. Some embodiments provide unexpected results in electromigration reliability in regards to activation energy and/or mean time to failure.
    Type: Application
    Filed: November 12, 2002
    Publication date: July 24, 2003
    Inventors: Stephen T. Chambers, Valery M. Dubin, Andrew W. Ott, Christine S. Hau-Riege
  • Patent number: 6518184
    Abstract: A method, apparatus, system, and machine-readable medium for an interconnect structure in a semiconductor device and its method of formation is disclosed. Embodiments comprise a carbon-doped and silicon-doped interconnect having a concentration of silicon to avoid to forming a copper silicide layer between an interconnect and a passivation layer. Some embodiments provide unexpected results in electromigration reliability in regards to activation energy and/or mean time to failure.
    Type: Grant
    Filed: January 18, 2002
    Date of Patent: February 11, 2003
    Assignee: Intel Corporation
    Inventors: Stephen T. Chambers, Valery M. Dubin, Andrew W. Ott, Christine S. Hau-Riege