Abstract: An integrated circuit (IC) package with an embedded heat spreader in a redistribution layer (RDL) is provided. IC packaging facilitates a high density package for ICs, including monolithic microwave integrated circuits (MMICs). However, IC packaging may result in reduced heat removal from an IC, decreasing radio frequency (RF) circuit performance. In an exemplary aspect, an IC package is provided which incorporates an embedded heat spreader within a dielectric layer of an RDL coupled to an IC die. The embedded heat spreader provides efficient heat transfer, robust RF performance, and operation through millimeter wave (mmW) frequencies, all in a miniature low-cost, low-profile surface mountable (SM) package.

Abstract: Semiconductor devices, and more particularly arrangements of fluorinated polymers with low dielectric loss for environmental protection in semiconductor devices are disclosed. Arrangements include conformal coatings or layers of fluorinated polymers that cover a semiconductor die on a package substrate of a semiconductor device. Such fluorinated polymer arrangements may also conformally coat various electrical connections for the semiconductor die, including wire bonds. Fluorinated polymers with low dielectric constants and low moisture permeability may thereby provide reduced moisture ingress in semiconductor devices while also reducing the impact of associated dielectric loss.

Abstract: The present disclosure relates to a semiconductor package with a thermally enhanced molding compound. The disclosed semiconductor package includes a module carrier having an upper surface, a die formed over the upper surface of the module carrier, and a thermally enhanced molding compound component formed over the upper surface of module carrier to encapsulate the die. Herein, the thermally enhanced molding compound is formed from a molding compound mixed with a thermal additive and has no air pockets or voids. The thermal additive includes a number of carbon flakes or a number of carbon spherical particles. The thermal additive has a thermal conductivity larger than 450 W/m·K and an electrical resistivity larger than 90 ??.cm. In one embodiment, the thermal additive includes a number of graphene flakes, a number of graphene particles, a number of graphite flakes, or a number of graphite particles.

Abstract: An integrated circuit (IC) package with an embedded heat spreader in a redistribution layer (RDL) is provided. IC packaging facilitates a high density package for ICs, including monolithic microwave integrated circuits (MMICs). However, IC packaging may result in reduced heat removal from an IC, decreasing radio frequency (RF) circuit performance. In an exemplary aspect, an IC package is provided which incorporates an embedded heat spreader within a dielectric layer of an RDL coupled to an IC die. The embedded heat spreader provides efficient heat transfer, robust RF performance, and operation through millimeter wave (mmW) frequencies, all in a miniature low-cost, low-profile surface mountable (SM) package.

Abstract: A die attach system includes a substrate that has scored grooves or into which stud bumps on a die are then inserted. The additional surface area and flow of the stud bumps into the trenches creates a strong mechanical bond that may withstand repeated thermal cycling. In a further exemplary aspect, the substrate may be covered in a first material, the stud bumps may be made from the same first material, a die attachment material may be made from the same first material, and a bottom layer of the die may be made from the same material. This material homogeneity allows for more uniform expansion and contraction during thermal cycling, preventing failure of the mechanical bond.

Abstract: An integrated circuit (IC) package with an embedded heat spreader in a redistribution layer (RDL) is provided. IC packaging facilitates a high density package for ICs, including monolithic microwave integrated circuits (MMICs). However, IC packaging may result in reduced heat removal from an IC, decreasing radio frequency (RF) circuit performance. In an exemplary aspect, an IC package is provided which incorporates an embedded heat spreader within a dielectric layer of an RDL coupled to an IC die. The embedded heat spreader provides efficient heat transfer, robust RF performance, and operation through millimeter wave (mmW) frequencies, all in a miniature low-cost, low-profile surface mountable (SM) package.

Abstract: RF devices, and more particularly RF devices with photo-imageable polymers for high frequency enhancements and related methods are disclosed. High frequency enhancements are realized by providing air cavities registered with one or more operating portions of RF devices. The air cavities are formed by photo-imageable polymer structures that provide separation from high dielectric constant materials associated with sealing materials, such as overmold materials, that are typically used for environmental and/or mechanical protection in RF devices. Related methods are disclosed that include forming the photo-imageable polymer structures and corresponding air cavities through various lamination and patterning of photo-imageable polymer layers. Further radiation hardening steps are disclosed that may be applied to the photo-imageable polymer structures after air cavities are formed to promote improved structural integrity of the air cavities during subsequent fabrication steps and during operation of the RF devices.

Abstract: Semiconductor devices, and more particularly arrangements of fluorinated polymers with low dielectric loss for environmental protection in semiconductor devices are disclosed. Arrangements include conformal coatings or layers of fluorinated polymers that cover a semiconductor die on a package substrate of a semiconductor device. Such fluorinated polymer arrangements may also conformally coat various electrical connections for the semiconductor die, including wire bonds. Fluorinated polymers with low dielectric constants and low moisture permeability may thereby provide reduced moisture ingress in semiconductor devices while also reducing the impact of associated dielectric loss.

Abstract: Improved structures for spatial power-combining devices are disclosed. A spatial power-combining device includes a plurality of amplifier assemblies and each amplifier assembly includes a body structure that supports an input antenna structure, an amplifier, and an output antenna structure. According to embodiments disclosed herein, the body structure comprises a material that is configured to provide the spatial power-combining device with reduced weight while maintaining good thermal dissipation for heat generated by the amplifiers. In certain embodiments, the body structure may comprise an allotrope of carbon such as graphite or graphene, among others. In certain embodiments, the body structure may include one or more thermal vias configured to dissipate heat from the amplifier.

Abstract: A method includes the steps of fabricating one or more semiconductor devices on a semiconductor wafer and depositing one or more conformal organic environmental protection layers over the semiconductor wafer using a vapor deposition process. By depositing the one or more conformal organic environmental protection layers using a vapor deposition process, thin film conformal organic environmental protection layers may be provided that offer excellent protection against water and oxygen ingress, thus increasing the ruggedness and reliability of the resulting semiconductor die.

Abstract: Improved structures for spatial power-combining devices are disclosed. A spatial power-combining device includes a plurality of amplifier assemblies and each amplifier assembly includes a body structure that supports an input antenna structure, an amplifier, and an output antenna structure. According to embodiments disclosed herein, the body structure comprises a material that is configured to provide the spatial power-combining device with reduced weight while maintaining good thermal dissipation for heat generated by the amplifiers. In certain embodiments, the body structure may comprise an allotrope of carbon such as graphite or graphene, among others. In certain embodiments, the body structure may include one or more thermal vias configured to dissipate heat from the amplifier.

Abstract: A method includes the steps of fabricating one or more semiconductor devices on a semiconductor wafer and depositing one or more conformal organic environmental protection layers over the semiconductor wafer using a vapor deposition process. By depositing the one or more conformal organic environmental protection layers using a vapor deposition process, thin film conformal organic environmental protection layers may be provided that offer excellent protection against water and oxygen ingress, thus increasing the ruggedness and reliability of the resulting semiconductor die.

Abstract: A method includes the steps of fabricating one or more semiconductor devices on a semiconductor wafer and depositing one or more conformal organic environmental protection layers over the semiconductor wafer using a vapor deposition process. By depositing the one or more conformal organic environmental protection layers using a vapor deposition process, thin film conformal organic environmental protection layers may be provided that offer excellent protection against water and oxygen ingress, thus increasing the ruggedness and reliability of the resulting semiconductor die.

Abstract: A method includes the steps of fabricating one or more semiconductor devices on a semiconductor wafer and depositing one or more conformal organic environmental protection layers over the semiconductor wafer using a vapor deposition process. By depositing the one or more conformal organic environmental protection layers using a vapor deposition process, thin film conformal organic environmental protection layers may be provided that offer excellent protection against water and oxygen ingress, thus increasing the ruggedness and reliability of the resulting semiconductor die.

Abstract: A method includes the steps of fabricating one or more semiconductor devices on a semiconductor wafer and depositing one or more conformal organic environmental protection layers over the semiconductor wafer using a vapor deposition process. By depositing the one or more conformal organic environmental protection layers using a vapor deposition process, thin film conformal organic environmental protection layers may be provided that offer excellent protection against water and oxygen ingress, thus increasing the ruggedness and reliability of the resulting semiconductor die.

Abstract: A semiconductor device including a contact pad and circuit metallization on the surface of an integrated circuit (IC) chip comprises a stack of protection layers over the surface of the chip. The stack consists of a first inorganic layer (303, preferably silicon nitride) on the chip surface, followed by a polymer layer (306, preferably benzocyclobutene) on the first inorganic layer (303), and finally an outermost second inorganic layer (310, preferably silicon dioxide) on the polymer layer (303). A window (301a) in the stack of layers exposes the metallization (301) of the IC. A patterned seed metal layer (307, preferably copper) is on the metallization (301) in the window and on the second inorganic layer (310) around the window. A buffer metal layer (308, preferably copper) is positioned on the seed metal layer (307). A metal reflow element (309) is attached to the buffer metal (308).

Abstract: A metal structure (600) for a bonding pad on integrated circuit wafers, which have interconnecting metallization (101) protected by an insulating layer (102) and selectively exposed by windows in the insulating layer. The structure comprises a patterned seed metal layer (104) positioned on the interconnecting metallization exposed by the window so that the seed metal establishes ohmic contact to the metallization as well as a practically impenetrable seal of the interface between the seed metal and the insulating layer. Further, a metal stud (301) is formed on the seed metal and aligned with the window. The metal stud is conformally covered by a barrier metal layer (501) and an outermost bondable metal layer (502).

Abstract: A semiconductor device including a contact pad and circuit metallization on the surface of an integrated circuit (IC) chip comprises a stack of protection layers over the surface of the chip. The stack consists of a first inorganic layer (303, preferably silicon nitride) on the chip surface, followed by a polymer layer (306, preferably benzocyclobutene) on the first inorganic layer (303), and finally an outermost second inorganic layer (310, preferably silicon dioxide) on the polymer layer (303). A window (301a) in the stack of layers exposes the metallization (301) of the IC. A patterned seed metal layer (307, preferably copper) is on the metallization (301) in the window and on the second inorganic layer (310) around the window. A buffer metal layer (308, preferably copper) is positioned on the seed metal layer (307). A metal reflow element (309) is attached to the buffer metal (308).

Abstract: A metal structure (600) for a bonding pad on integrated circuit wafers, which have interconnecting metallization (101) protected by an insulating layer (102) and selectively exposed by windows in the insulating layer. The structure comprises a patterned seed metal layer (104) positioned on the interconnecting metallization exposed by the window so that the seed metal establishes ohmic contact to the metallization as well as a practically impenetrable seal of the interface between the seed metal and the insulating layer. Further, a metal stud (301) is formed on the seed metal and aligned with the window. The metal stud is conformally covered by a barrier metal layer (501) and an outermost bondable metal layer (502).

Abstract: A method for preparing a bonding pad on an integrated circuit wafer by the steps of depositing a conductive seed layer (104) on the bonding pad; depositing a metal layer (301, 302, and 303) over a portion of the conductive seed layer; and immersing the wafer in an etchant solution (501) to remove the portion of the seed layer not covered by the metal layer. The etchant solution contains a chelating agent that bonds ions from the seed layer. When the seed layer is copper or a refractory metal, and the metal layer is gold or palladium, the preferred chelating agent is selected from, but is not limited to, but is not limited to, the families of ethylenediaminetetraacetic acids (EDTA), 8-hydroxy-quinolines, including 8-hydroxy-quinoline-5-sulfonic acid, porphyrins, and phthalocyanines.