Abstract: The application relates to a power semiconductor device, including: a semiconductor body having a front side coupled to a frontside metallization and a backside coupled to a backside metallization; and an active region with a plurality of transistor cells. The frontside metallization includes a first load terminal structure and a control terminal structure. At least one of the first layer and the second layer is laterally segmented, with a first segment being part of the first load terminal structure and a second segment being part of the control terminal structure.

Abstract: A method of manufacturing a semiconductor device includes forming a wiring metal layer structure; forming a dielectric layer structure arranged directly on the wiring metal layer structure; and forming a bonding pad metal layer structure arranged, at least partially, directly on the dielectric layer structure, wherein a layer thickness of the dielectric layer structure ranges from 1% to 30% of a layer thickness of the wiring metal layer structure, wherein the wiring metal layer structure and the bonding pad metal structure are electrically connected through openings in the dielectric layer structure.

Abstract: A semiconductor device is proposed. The semiconductor device includes a wiring metal layer structure. The semiconductor device further includes a dielectric layer structure arranged directly on the wiring metal layer structure. The semiconductor device further includes a bonding pad metal layer structure arranged, at least partly, directly on the dielectric layer structure. A layer thickness of the dielectric layer structure ranges from 1% to 30% of a layer thickness of the wiring metal layer structure. The wiring metal layer structure and the bonding pad metal structure are electrically connected through openings in the dielectric layer structure.

Abstract: A semiconductor device is proposed. The semiconductor device includes a wiring metal layer structure. The semiconductor device further includes a dielectric layer structure arranged directly on the wiring metal layer structure. The semiconductor device further includes a bonding pad metal layer structure arranged, at least partly, directly on the dielectric layer structure. A layer thickness of the dielectric layer structure ranges from 1% to 30% of a layer thickness of the wiring metal layer structure. The wiring metal layer structure and the bonding pad metal structure are electrically connected through openings in the dielectric layer structure.

Abstract: In one aspect, a method of forming a silicon-insulator layer is provided. The method includes arranging a silicon structure in a plasma etch process chamber and applying a plasma to the silicon structure in the plasma etch process chamber at a temperature of the silicon structure equal to or below 100° C. The plasma includes a component and a halogen derivate, thereby forming the silicon-insulator layer. The silicon-insulator layer includes silicon and the component. In another aspect, a semiconductor device is provided having a silicon-insulator layer formed by the method.

Abstract: In one aspect, a method of forming a silicon-insulator layer is provided. The method includes arranging a silicon structure in a plasma etch process chamber and applying a plasma to the silicon structure in the plasma etch process chamber at a temperature of the silicon structure equal to or below 100° C. The plasma includes a component and a halogen derivate, thereby forming the silicon-insulator layer. The silicon-insulator layer includes silicon and the component. In another aspect, a semiconductor device is provided having a silicon-insulator layer formed by the method.

Abstract: A method for forming a semiconductor device and semiconductor device is disclosed. In one example, the method includes forming a silicone layer on a semiconductor die. The method further includes plasma treating a silicone surface of the silicone layer. A surfactant is deposited on the plasma-treated silicone surface of the silicone layer to obtain a silicone surface at least partly covered by surfactant. A mold is formed on the silicone surface at least partly covered by surfactant. The surfactant includes surfactant molecules comprising an inorganic skeleton terminated by organic compounds.

Abstract: A method for forming a semiconductor device and semiconductor device is disclosed. In one example, the method includes forming a silicone layer on a semiconductor die. The method further includes plasma treating a silicone surface of the silicone layer. A surfactant is deposited on the plasma-treated silicone surface of the silicone layer to obtain a silicone surface at least partly covered by surfactant. A mold is formed on the silicone surface at least partly covered by surfactant. The surfactant includes surfactant molecules comprising an inorganic skeleton terminated by organic compounds.