Patents by Inventor Christoffer G Greisen

Christoffer G Greisen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor-based sub-mounts for optoelectronic devices with conductive paths
    Patent number: 8357934
    Abstract: The disclosure facilitates testing and binning of multiple LED chip or other optoelectronic chip packages fabricated on a single semiconductor wafer. The testing can take place prior to dicing. For example, in one aspect, metallization on the front-side of a semiconductor wafer electrically connects together cathode pads (or anode pads) of adjacent sub-mounts such that the cathode pads (or anode pads) in a given column of sub-mounts are electrically connected together. Likewise, metallization on the back-side of the wafer electrically connects together anode pads (or cathode pads) of adjacent sub-mounts such that the anode pads (or cathode pads) in a given row of sub-mounts are electrically connected together. Probe pads, which can be located one or both sides of the wafer, are electrically connected to respective ones of the rows or columns.
    Type: Grant
    Filed: November 3, 2010
    Date of Patent: January 22, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Christoffer G. Greisen
  • SEMICONDUCTOR-BASED SUB-MOUNTS FOR OPTOELECTRONIC DEVICES WITH CONDUCTIVE PATHS
    Publication number: 20110101350
    Abstract: The disclosure facilitates testing and binning of multiple LED chip or other optoelectronic chip packages fabricated on a single semiconductor wafer. The testing can take place prior to dicing. For example, in one aspect, metallization on the front-side of a semiconductor wafer electrically connects together cathode pads (or anode pads) of adjacent sub-mounts such that the cathode pads (or anode pads) in a given column of sub-mounts are electrically connected together. Likewise, metallization on the back-side of the wafer electrically connects together anode pads (or cathode pads) of adjacent sub-mounts such that the anode pads (or cathode pads) in a given row of sub-mounts are electrically connected together. Probe pads, which can be located one or both sides of the wafer, are electrically connected to respective ones of the rows or columns.
    Type: Application
    Filed: November 3, 2010
    Publication date: May 5, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Christoffer G. Greisen
  • Semiconductor-based sub-mounts for optoelectronic devices with conductive paths to facilitate testing and binning
    Patent number: 7838878
    Abstract: The disclosure facilitates testing and binning of multiple LED chip or other optoelectronic chip packages fabricated on a single semiconductor wafer. The testing can take place prior to dicing. For example, in one aspect, metallization on the front-side of a semiconductor wafer electrically connects together cathode pads (or anode pads) of adjacent sub-mounts such that the cathode pads (or anode pads) in a given column of sub-mounts are electrically connected together. Likewise, metallization on the back-side of the wafer electrically connects together anode pads (or cathode pads) of adjacent sub-mounts such that the anode pads (or cathode pads) in a given row of sub-mounts are electrically connected together. Probe pads, which can be located one or both sides of the wafer, are electrically connected to respective ones of the rows or columns.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: November 23, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Christoffer G Greisen
  • SEMICONDUCTOR-BASED SUB-MOUNTS FOR OPTOELECTRONIC DEVICES WITH CONDUCTIVE PATHS TO FACILITATE TESTING AND BINNING
    Publication number: 20100244055
    Abstract: The disclosure facilitates testing and binning of multiple LED chip or other optoelectronic chip packages fabricated on a single semiconductor wafer. The testing can take place prior to dicing. For example, in one aspect, metallization on the front-side of a semiconductor wafer electrically connects together cathode pads (or anode pads) of adjacent sub-mounts such that the cathode pads (or anode pads) in a given column of sub-mounts are electrically connected together. Likewise, metallization on the back-side of the wafer electrically connects together anode pads (or cathode pads) of adjacent sub-mounts such that the anode pads (or cathode pads) in a given row of sub-mounts are electrically connected together. Probe pads, which can be located one or both sides of the wafer, are electrically connected to respective ones of the rows or columns.
    Type: Application
    Filed: March 24, 2009
    Publication date: September 30, 2010
    Applicant: Hymite A/S
    Inventor: Christoffer G. Greisen